AD7851
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REV. B
STATUS REGISTER
The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the
bits in the status register is described below. The power-up status of all bits is 0.
WRITE TO CONTROL REGISTER
SETTING RDSLT0 = RDSLT1 = 1
READ STATUS REGISTER
START
Figure 6. Flowchart for Reading the Status Register
MSB
ZERO BUSY ZERO ZERO ZERO ZERO PMGT1 PMGT0
RDSLT1 RDSLT0
2/3 MODE
X CALMD CALSLT1 CALSLT0 STCAL
LSB
Status Register Bit Function Descriptions
Bit No. Mnemonic Comment
15 ZERO This bit is always 0.
14 BUSY Conversion/Calibration Busy Bit. When this bit is 1, this indicates that there is a conversion or calibration
in progress. When this bit is 0, there is no conversion or calibration in progress.
13 ZERO These four bits are always 0.
12 ZERO
11 ZERO
10 ZERO
9PMGT1 Power Management Bits. These bits along with the SLEEP pin will indicate whether the part is in a power-
8PMGT0 down mode. (See Table VI in the Power-Down Options section for description.)
7 RDSLT1 Both these bits are always 1 indicating it is the status register that is being read. (See Table II.)
6 RDSLT0
52/3 MODE Interface Mode Select Bit. With this bit 0, the device is in Interface Mode 2. With this bit 1, the device is in
Interface Mode 1. This bit is reset to 0 after every read cycle.
4X Don’t care bit.
3 CALMD Calibration Mode Bit. A 0 in this bit indicates self-calibration is selected, and 1 in this bit indicates a system
calibration is selected (see Table III).
2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a calibration is in
1 CALSLT0 progress and as a 0 if there is no calibration in progress. The CALSLT1 and CALSLT0 bits indicate which
0 STCAL of the calibration registers are addressed for reading and writing (see the Calibration Registers section for
more details)
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REV. B
AD7851
CALIBRATION REGISTERS
The AD7851 has 10 calibration registers in all, 8 for the DAC, 1 for the offset, and 1 for gain. Data can be written to or read from all
10 calibration registers. In self- and system calibration, the part automatically modifies the calibration registers; only if the user needs
to modify the calibration registers should an attempt be made to read from and write to the calibration registers.
Addressing the Calibration Registers
The calibration selection bits in the control register, CALSLT1 and CALSLT0, determine which of the calibration registers are
addressed (see Table IV). The addressing applies to both the read and write operations for the calibration registers. The user
should not attempt to read from and write to the calibration registers at the same time.
Table IV. Calibration Register Addressing
CALSLT1 CALSLT0 This Combination Addresses the
0 0Gain (1), Offset (1) and DAC Registers (8). Ten registers in total.
0 1Gain (1) and Offset (1) Registers. Two registers in total.
1 0Offset Register. One register in total.
1 1Gain Register. One register in total.
Writing to/Reading from the Calibration Registers
For writing to the calibration registers, a write to the control reg-
ister is required to set the CALSLT0 and CALSLT1 bits. For
reading from the calibration registers, a write to the control regis-
ter is required to set the CALSLT0 and CALSLT1 bits, but also
to set the RDSLT1 and RDSLT0 bits to 10 (this addresses the
calibration registers for reading). The calibration register pointer
is reset on writing to the control register setting the CALSLT1
and CALSLT0 bits, or upon completion of all the calibration
register write/read operations. When reset, it points to the first
calibration register in the selected write/read sequence. The cali-
bration register pointer will point to the gain calibration register
upon reset in all but one case, this case being where the offset
calibration register is selected on its own (CALSLT1 = 1,
CALSLT0 = 0). Where more than one calibration register is being
accessed, the calibration register pointer will be automatically
incremented after each calibration register write/read operation.
The order in which the 10 calibration registers are arranged is
shown in Figure 7. The user may abort at any time before all
the calibration register write/read operations are completed,
and the next control register write operation will reset the cali-
bration register pointer. The flowchart in Figure 8 shows the
sequence for writing to the calibration registers and Figure 9
shows the sequence for reading.
CAL REGISTER
ADDRESS POINTER
CALIBRATION REGISTERS
GAIN REGISTER
OFFSET REGISTER
DAC 1st MSB REGISTER
DAC 8th MSB REGISTER
(1)
(2)
(3)
(10)
CALIBRATION REGISTER ADDRESS POINTER POSITION IS
DETERMINED BY THE NUMBER OF CALIBRATION REGISTERS
ADDRESSED AND THE NUMBER OF READ/WRITE OPERATIONS.
Figure 7. Calibration Register Arrangement
When reading from the calibration registers there will always be
two leading zeros for each of the registers. When operating in
Serial Interface Mode 1, the read operations to the calibration
registers cannot be aborted. The full number of read operations
must be completed (see the Serial Interface Summary section
for more detail).
START
WRITE TO CAL REGISTER
(ADDR1 = 1, ADDR0 = 0)
FINISHED
LAST
REGISTER
WRITE
OPERATION
OR
ABORT
?
YES
NO
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
WRITE TO CONTROL REGISTER SETTING STCAL = 0
AND CALSLT1, CALSLT0 = 00, 01, 10, 11
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
Figure 8. Flowchart for Writing to the Calibration Registers
AD7851
–14–
REV. B
FINISHED
LAST
REGISTER
WRITE
OPERATION
OR
ABORT
?
YES
NO
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
READ CAL REGISTER
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1,
RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11
START
Figure 9. Flowchart for Reading from the
Calibration Registers
Adjusting the Offset Calibration Register
The offset calibration register contains 16 bits, 2 leading 0s, and
14 data bits. By changing the contents of the offset register, dif-
ferent amounts of offset on the analog input signal can be com-
pensated for. Increasing the number in the offset calibration
register compensates for the negative offset on the analog input
signal, and decreasing the number in the offset calibration regis-
ter compensates for the positive offset on the analog input signal.
The default value of the offset calibration register is approxi-
mately 0010 0000 0000 0000. This is not an exact value, but the
value in the offset register should be close to this value. Each of
the 14 data bits in the offset register is binary weighted; the MSB
has a weighting of 5% of the reference voltage, the MSB-1 has a
weighting of 2.5%, the MSB-2 has a weighting of 1.25%, and so
on down to the LSB which has a weighting of 0.0006%.
This gives a resolution of ±0.0006% of V
REF
approximately.
More accurately the resolution is ± (0.05 × V
REF
)/2
13
V =
±0.015 mV, with a 2.5 V reference. The maximum offset that
can be compensated for is ±5% of the reference voltage, which
equates to ±125 mV with a 2.5 V reference and ±250 mV with
a 5 V reference.
Q. If a +20 mV offset is present in the analog input signal and
the reference voltage is 2.5 V, what code needs to be written
to the offset register to compensate for the offset?
A. The 2.5 V reference implies that the resolution in the off-
set register is 5% × 2.5 V/2
13
= 0.015 mV. 20 mV/
0.015 mV = 1310.72; rounding to the nearest number gives
1311. In binary terms this is 0101 0001 1111, therefore
decrease the offset register by 0101 0001 1111.
This method of compensating for offset in the analog input signal
allows for fine-tuning the offset compensation. If the offset on the
analog input signal is known, there will be no need to apply the
offset voltage to the analog input pins to do a system calibration.
The offset compensation can take place in software.
Adjusting the Gain Calibration Register
The gain calibration register contains 16 bits, 2 leading 0s, and
14 data bits. The data bits are binary weighted as in the offset
calibration register. The gain register value is effectively multi-
plied by the analog input to scale the conversion result over the
full range. Increasing the gain register compensates for a
smaller analog input range and decreasing the gain register
compensates for a larger input range. The maximum analog
input range that the gain register can compensate for is 1.025
times the reference voltage, and the minimum input range is
0.975 times the reference voltage.

AD7851ARSZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 14B 333kSPS Serial Sampling
Lifecycle:
New from this manufacturer.
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