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AD7851ARSZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
AD7851
–24–
REV. B
SERIAL INTERFACE SUMMARY
Table IX details the five interface modes and the serial clock
edges from which the data is clocked out by the AD7851
(DOUT edge) and that the data is latched in on (DIN edge).
The logic level of the POLARITY pin is shown and it is clear
that this reverses the edges.
In Interface Modes 4 and 5 the SYNC always clocks out the
first data bit and SCLK will clock out the subsequent bits.
In Interface Modes 1, 2, and 3 the SYNC is gated with the SCLK
and the POLARITY pin. Thus, the SYNC may clock out the
MSB of data. Subsequent bits will be clocked out by the serial
clock, SCLK. The conditions for the SYNC clocking out the
MSB of data is as follows.
With the POLARITY pin high, the falling edge of SYNC will
clock out the MSB if the serial clock is low when the SYNC
goes low.
With the POLARITY pin low, the falling edge of SYNC will
clock out the MSB if the serial clock is high when the SYNC
goes low.
Table IX. SCLK Active Edge for Different Interface Modes
Interface POLARITY DOUT DIN
Mode Pin Edge Edge
1, 2, 3 0 SCLK ↑ SCLK ↓
1SCLK ↓ SCLK ↑
4, 5 0 SCLK ↓ SCLK ↑
1SCLK ↑ SCLK ↓
Resetting the Serial Interface
When writing to the part via the DIN line there is the possibility
of writing data into the incorrect registers, such as the test regis-
ter for instance, or writing the incorrect data and corrupting the
serial interface. The SYNC pin acts as a reset. Bringing the
SYNC pin high resets the internal shift register. The first data
bit after the next SYNC falling edge will now be the first bit of
a new 16-bit transfer. It is also possible that the test register
contents were altered when the interface was lost. Therefore,
once the serial interface is reset, it may be necessary to write
the 16-bit word 0100 0000 0000 0010 to restore the test regis-
ter to its default value. Now the part and serial interface are
completely reset. It is always useful to retain the ability to pro-
gram the SYNC line from a port of the µController/DSP to have
the ability to reset the serial interface.
Table X summarizes the interface modes provided by the
AD7851. It also outlines the various µP/µC to which the par-
ticular interface is suited.
The interface mode is determined by the serial mode selection
Pins SM1 and SM2. Interface Mode 2 is the default mode.
Note that Interface Mode 1 and 2 have the same combination of
SM1 and SM2. Interface Mode 1 may only be set by program-
ming the control register (see the Control Register section).
External SCLK and SYNC signals (SYNC may be hardwired
low) are required for Interfaces Modes 1, 2, and 3. In Interface
Modes 4 and 5, the AD7851 generates the SCLK and SYNC.
Some of the more popular µProcessors, µControllers, and the
DSP machines that the AD7851 will interface to directly are
mentioned here. This does not cover all µCs, µPs, and DSPs. The
interface mode of the AD7851 that is mentioned here for a
specific µC, µP, or DSP is only a guide and in most cases another
interface mode may work just as well.
A more detailed timing description on each of the interface
modes follows.
Table X. Interface Mode Description
SM1 SM2 ␮Processor Interface
Pin Pin ␮Controller Mode
00 8XC51 1 (2-Wire)
8XL51 DIN Is an Input/
PIC17C42 Output Pin
00 68HC11 2 (3-Wire, SPI/QSPI)
68L11 Default Mode
01 68HC16 3 (QSPI)
PIC16C64 External Serial
ADSP-21xx Clock, SCLK, and
DSP56000 External Frame Sync,
DSP56001 SYNC Are Required
DSP56002
DSP56L002
TMS320C30
10 68HC16 4 (DSP Is Slave)
AD7851 Generates a
Noncontinuous
(16 Clocks) Serial
Clock, SCLK, and the
Frame Sync, SYNC
11 ADSP-21xx 5 (DSP Is Slave)
DSP56000 AD7851 Generates a
DSP56001 Continuous Serial
DSP56002 Clock, SCLK, and the
DSP56L002 Frame Sync, SYNC
TMS320C20
TMS320C25
TMS320C30
TMS320C5X
TMS320LC5X
–25–
REV. B
AD7851
DB15 DB0
DB0
DB15
t
3
DIN (I/O)
t
3
t
11
t
6
116 161
t
5A
t
12
DIN BECOMES AN INPUT
THREE-STATE
t
6
t
11
DIN BECOMES AN OUTPUT
t
3
= –0.4 t
SCLK
MIN (NONCONTINUOUS SCLK) ⴞ0.4 t
SCLK
MIN/MAX (CONTINUOUS SCLK),
t
6
= 45 MAX, t
7
= 30ns
MIN, t
8
= 20
MIN
POLARITY PIN
LOGIC HIGH
SYNC (I/P)
SCLK (I/P)
t
8
t
14
t
7
DATA WRITE
DATA READ
Figure 33. Timing Diagram for Read/Write Operation with DIN as an Input/Output (Interface Mode 1, SM1 = SM2 = 0)
DB15 DB0DB0 DB15
DIN (I/O)
t
6
= 45 MAX, t
7
= 30ns
MIN, t
8
= 20
MIN,
t
13
= 90 MAX, t
14
= 50ns
MAX
6
116 161
t
13
t
6
DIN BECOMES AN INPUT
t
6
POLARITY PIN
LOGIC HIGH
SCLK (I/P)
t
8
t
14
t
7
DATA WRITE
DATA READ
Figure 34. Timing Diagram for Read/Write Operation with DIN as an Input/Output and
SYNC
Input Tied Low
(Interface Mode 1, SM1 = SM2 = 0)
DETAILED TIMING SECTION
Mode 1 (2-Wire 8051 Interface)
The read and writing takes place on the DIN line and the conver-
sion is initiated by pulsing the CONVST pin (note that in every
write cycle the 2/3 MODE bit must be set to 1). The conversion
may be started by setting the CONVST bit in the control register
to 1 instead of using the CONVST line.
Below in Figure 33 and in Figure 34 are the timing diagrams for
Interface Mode 1 in the 2-wire interface mode. Here the DIN pin
is used for both input and output as shown. The SYNC input is
level-triggered active low and can be pulsed (Figure 33) or can be
constantly low (Figure 34).
In Figure 33, the part samples the input data on the rising edge
of SCLK. After the 16th rising edge of SCLK, the DIN is con-
figured as an output. When the SYNC is taken high, the DIN is
three-stated. Taking SYNC low disables the three-state on the
DIN pin and the first SCLK falling edge clocks out the first data
bit. Once the 16 clocks have been provided, the DIN pin will
automatically revert back to an input after a time t
14
. Note that a
continuous SCLK shown by the dotted waveform in Figure 33
can be used provided the SYNC is low for only 16 clock pulses
in each of the read and write cycles. The POLARITY pin may
be used to change the SCLK edge which the data is sampled on
and clocked out on.
In Figure 34, the SYNC line is tied low permanently, which
results in a different timing arrangement. With SYNC tied low
permanently, the DIN pin will never be three-stated. The 16th
rising edge of SCLK configures the DIN pin as an input or an
output as shown in the diagram. Here no more than 16 SCLK
pulses must occur for each of the read and write operations.
If reading from and writing to the calibration registers in this
interface mode, all the selected calibration registers must be
read from or written to. The read and write operations cannot
be aborted. When reading from the calibration registers, the
DIN pin will remain as an output for the full duration of all
the calibration register read operations. When writing to the
calibration registers, the DIN pin will remain as an input for
the full duration of all the calibration register write operations.
AD7851
–26–
REV. B
Mode 2 (3-Wire SPI/QSPI Interface Mode)
Default Interface Mode
Figure 35 shows the timing diagram for Interface Mode 2 which
is the SPI/QSPI interface mode. Here the SYNC input is active
low and may be pulsed or tied permanently low. If SYNC is
permanently low, 16 clock pulses must be applied to the SCLK
pin for the part to operate correctly, and with a pulsed SYNC
input a continuous SCLK may be applied provided SYNC is
low for only 16 SCLK cycles. In Figure 35, the SYNC going
low disables the three-state on the DOUT pin. The first falling
edge of the SCLK after the SYNC going low clocks out the first
leading zero on the DOUT pin. The DOUT pin is three-stated
again a time t
12
after the SYNC goes high. With the DIN pin,
the data input has to be set up a time t
7
before the SCLK rising
edge as the part samples the input data on the SCLK rising edge
in this case. The POLARITY pin may be used to change the
SCLK edge which the data is sampled on and clocked out on. If
resetting the interface is required, the SYNC must be taken high
and then low.
DB0DB10
THREE-STATE
THREE-STATE
DB12
DB13DB14DB15 DB11
DB12 DB0DB10DB11DB13DB14DB15
t
3
= –0.4 t
CLKIN
MIN (NONCONTINUOUS SCLK) ±0.4 t
SCLK
MIN/MAX (CONTINUOUS SCLK),
t
6
= 45ns MAX, t
7
= 30ns
MIN, t
8
= 20ns MIN, t
11
= 30ns MIN (NONCONTINUOUS SCLK),
30/0.4 t
SCLK
= ns
MIN/MAX (CONTINUOUS SCLK)
POLARITY PIN
LOGIC HIGH
SYNC (I/P)
162345
16
SCLK (I/P)
t
9
t
5
t
11
t
3
t
10
t
12
DOUT (O/P)
t
8
DIN (I/P)
t
6
t
7
t
8
t
6
Figure 35. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation with DIN Input, DOUT Output, and
SYNC
Input
(SM1 = SM2 = 0)
t
3
= –0.4 t
CLKIN
MIN (NONCONTINUOUS SCLK) ±0.4 t
SCLK
MIN/MAX (CONTINUOUS SCLK),
t
6
= 45ns MAX, t
7
= 30ns
MIN, t
8
= 20ns MIN, t
11
= 30ns MIN
DB0DB10
THREE-STATE
THREE-STATE
DB12DB13DB14DB15 DB11
DB12 DB0DB10DB11DB13DB14DB15
POLARITY PIN
LOGIC HIGH
SYNC (I/P)
162345
16
SCLK (I/P)
t
9
t
5
t
11
t
3
t
10
t
12
DOUT (O/P)
t
8
DIN (I/P)
t
6
t
7
t
8
t
6
Figure 36. QSPI Mode 3 Timing Diagram for Read/Write Operation with
SYNC
Input Edge Triggered (SM1 = 0, SM2 = 1)
Mode 3 (QSPI Interface Mode)
Figure 36 shows the timing diagram for Interface Mode 3. In
this mode, the DSP is the master and the part is the slave. Here
the SYNC input is edge triggered from high to low, and the 16
clock pulses are counted from this edge. Because the clock
pulses are counted internally, the SYNC signal does not have to
go high after the 16th SCLK rising edge as shown by the dotted
SYNC line. Thus a frame sync that gives a high pulse of one
SCLK cycle minimum duration at the beginning of the read/
write operation may be used. The rising edge of SYNC enables
the three-state on the DOUT pin. The falling edge of SYNC
disables the three-state on the DOUT pin, and data is clocked
out on the falling edge of SCLK. Once SYNC goes high, the
three-state on the DOUT pin is enabled. The data input is
sampled on the rising edge of SCLK and thus has to be valid a
time t
7
before this rising edge. The POLARITY pin may be
used to change the SCLK edge which the data is sampled on
and clocked out on. If resetting the interface is required, the
SYNC must be taken high and then low.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

AD7851ARSZ-REEL

Mfr. #:
Buy AD7851ARSZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 14B 333kSPS Serial Sampling
Lifecycle:
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