–31–
REV. B
AD7851
(8XC51/L51)
/PIC17C42
P3.0/DT
P3.1/CK
AD7851
CONVST
CLKIN
SCLK
DIN
SYNC
SM1
SM2
POLARITY
OPTIONAL
7MHz/6MHz
BUSY
(INT0/P3.2)/INT
DGND FOR 8XC51/L51
DV
DD
FOR PIC17C42
MASTER
SLAVE
OPTIONAL
Figure 45. 8XC51/PIC17C42 Interface
AD7851 to 68HC11/16/L11/PIC16C42 Interface
Figure 46 shows the AD7851 SPI/QSPI interface to the
68HC11/16/L11/PIC16C42. The SYNC line is not used and is
tied to DGND. The µController is configured as the master by
setting the MSTR bit in the SPCR to 1, and thus provides the
serial clock on the SCK pin. For all the µControllers, the CPOL
bit is set to 1, and for the 68HC11/16/L11, the CPHA bit is set
to 1. The CLKIN and CONVST signals can be supplied from
the µController or from separate sources. The BUSY signal can
be used as an interrupt to tell the µController when the conver-
sion is finished, then the reading and writing can take place. If
required, the reading and writing can take place during conver-
sion and there will be no need for the BUSY signal in this case.
For no writing to the part then the DIN pin can be tied perma-
nently low. For the 68HC16 and the QSPI interface, the SM2
pin should be tied high and the SS line tied to the SYNC pin.
The microsequencer on the 68HC16 QSPI port can be used for
performing a number of read and write operations independent
of the CPU and storing the conversion results in memory with-
out taxing the CPU. The typical sequence of events would be
writing to the control register via the DIN line setting a conversion
start and at the same time reading data from the previous conver-
sion on the DOUT line, wait for the conversion to be finished
(3.25 µs with 6 MHz CLKIN), and then repeat the sequence. The
maximum serial frequency will be determined by the data access
and hold times of the µControllers and the AD7851.
68HC11/16/
L11/PIC16C42
SCK
SS
AD7851
CONVST
CLKIN
SCLK
DOUT
BUSY
SM1
SM2
POLARITY
OPTIONAL
7MHz/6MHz
SYNC
MISO
DIN AT DGND FOR
NO WRITING TO PART
MASTER
SLAVE
DIN
DV
DD
OPTIONAL
IRQ
MOSI
DV
DD
FOR HC11, SPI
DGND FOR HC16, QSPI
DV
DD
SPI
HC16, QSPI
Figure 46. 68HC11 and 68HC16 Interface
MICROPROCESSOR INTERFACING
In many applications, the user may not require the facility of
writing to the on-chip registers. The user may just want to
hardwire the relevant pins to the appropriate levels and read
the conversion result. In this case, the DIN pin can be tied low
so that the on-chip registers are never used. Now the part will
operate as a nonprogrammable analog-to-digital converter where
the CONVST is applied, a conversion is performed, and the result
may be read using the SCLK to clock out the data from the output
register on to the DOUT pin. Note that the DIN pin cannot be
tied low when using the 2-wire interface mode of operation.
The SCLK can also be connected to the CLKIN pin if the user
does not want to have to provide separate serial and master
clocks in Interface Modes 1, 2, and 3. With this arrangement,
the SYNC signal must be low for 16 SCLK cycles in Interface
Modes 1 and 2 for the read and write operations. For Interface
Mode 3, the SYNC can be low for more than 16 SCLK cycles
for the read and write operations. Note that in Interface Modes 4
and 5 the CLKIN and SCLK cannot be tied together as the
SCLK is an output and the CLKIN is an input.
DIN
DOUT
SYNC
CONVST
CLKIN
SCLK
AD7851
7 MH z/6MHz
MASTER
CLOCK
SYNC SIGNAL
TO GATE
THE SCLK
SERIAL DATA
OUTPUT
CONVERSION
START
Figure 44. Simplified Interface Diagram with DIN
Grounded and SCLK Tied to CLKIN
AD7851 to 8XC51/PIC17C42 Interface
Figure 45 shows the AD7851 interface to the 8XC51/PIC17C42,
which only runs at 5 V. The 8XC51 is in Mode 0 operation.
This is a 2-wire interface consisting of the SCLK and the DIN
which acts as a bidirectional line. The SYNC is tied low. The
BUSY line can be used to give an interrupt driven system but
this would not normally be the case with the 8XC51/PIC17C42.
For the 8XC51, 12 MHz version, the serial clock will run at a
maximum of 1 MHz so that the serial interface to the AD7851
will only be running at 1 MHz. The CLKIN signal must be pro-
vided separately to the AD7851 from a port line on the 8XC51
or from a source other than the 8XC51. Here the SCLK cannot
be tied to the CLKIN as the 8XC51 only provides a noncon-
tinuous serial clock. The CONVST signal can be provided from
an external timer or conversion can be started in software if
required. The sequence of events would typically be writing to
the control register via the DIN line setting a conversion start
and the 2-wire interface mode (this would be performed in two
8-bit writes), wait for the conversion to be finished (3.25 µs with
6 MHz CLKIN), read the conversion result data on the DIN line
(this would be performed in two 8-bit reads), and then repeat the
sequence. The maximum serial frequency will be determined by
the data access and hold times of the 8XC51/PIC17C42 and the
AD7851.
