AD7851KNZ Datasheet AD7851KRZ, AD7851ARZ, AD7851ARSZ-REEL | P10-P12

–9–

REV. B

AD7851

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 CONVST Convert Start. Logic input. A low-to-high transition on this input puts the track-and-hold into its hold

mode and starts conversion. When this input is not used, it should be tied to DV

2 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL and

remains high until conversion is completed. BUSY is also used to indicate when the AD7851 has completed

its on-chip calibration sequence.

3 SLEEP Sleep Input/Low Power Mode. A Logic 0 initiates a sleep and all circuitry is powered down, including the

internal voltage reference, provided there is no conversion or calibration being performed. Calibration data

is retained. A Logic 1 results in normal operation. See Power-Down section for more details.

4 REF

/Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

REF

OUT

reference source for the analog-to-digital converter. The nominal reference voltage is 4.096 V and this appears

at the pin. This pin can be overdriven by an external reference or can be taken as high as AV

. When this

pin is tied to AV

, or when an externally applied reference approaches V

, then the C

REF1

pin should also

be tied to AV

5AV

Analog Positive Supply Voltage, 5.0 V ± 5%.

6, 12 AGND Analog Ground. Ground reference for track and hold, reference, and DAC.

REF1

Reference Capacitor (0.1 µF ceramic disc in parallel with a 470 nF tantalum). This external capacitor is

used as a charge source for the internal DAC. The capacitor should be tied between the pin and AGND.

REF2

Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip

reference. The capacitor should be tied between the pin and AGND.

9 AIN(+) Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above

at any time and cannot go below AIN(–) when the unipolar input range is selected.

10 AIN(–) Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above

at any time.

11 NC No Connect Pin.

13 AMODE Analog Mode Pin. This pin allows two different analog input ranges to be selected. A Logic 0 selects range

0 to V

REF

(i.e., AIN(+) – AIN(–) = 0 to V

REF

). In this case, AIN(+) cannot go below AIN(–) and AIN(–)

cannot go below AGND. A Logic 1 selects range –V

REF

/2 to +V

REF

/2 (i.e., AIN(+) – AIN(–) = –V

REF

/2 to

REF

/2). In this case, AIN(+) cannot go below AGND so that AIN(–) needs to be biased to +V

REF

/2 to

allow AIN(+) to go from 0 V to +V

REF

14 POLARITY Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will

reverse the active edge of the serial clock (SCLK). A Logic 1 means that the serial clock (SCLK) idles high

and a Logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and

Table IX for the SCLK active edges.

15 SM1 Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera-

tion as described in Table X.

16 SM2 Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera-

tion as described in Table X.

17 CAL Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A Logic 0 on this pin resets all

calibration control logic and initiates a calibration on its rising edge. There is the option of connecting a 10 nF

capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This input overrides

all other internal operations. If the autocalibration is not required, then this pin should be tied to a logic high.

18 DV

Digital Supply Voltage, 5.0 V ± 5%.

19 DGND Digital Ground. Ground reference point for digital circuitry.

20 DOUT Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.

21 DIN Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act as

an input pin or as a input and output pin depending on the serial interface mode the part is in (see Table X).

22 CLKIN Master Clock Signal for the Device (6 MHz or 7 MHz). Sets the conversion and calibration times.

23 SCLK Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the

type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and

SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin.

24 SYNC This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync

in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table X).

AD7851

–10–

REV. B

AD7851 ON-CHIP REGISTERS

The AD7851 powers up with a set of default conditions, and the user need not ever write to the device. In this case, the AD7851 will

operate as a read-only ADC. The AD7851 still retains the flexibility for performing a full power-down and a full self-calibration.

Note that the DIN pin should be tied to DGND for operating the AD7851 as a read-only ADC.

Extra features and flexibility, such as performing different power-down options, different types of calibrations, including system cali-

bration, and software conversion starts can be selected by writing to the part.

The AD7851 contains a control register, ADC output data register, status register, test register, and 10 calibration registers.

The control register is write-only, the ADC output data register and the status register are read-only, and the test and calibration

registers are both read/write registers. The test register is used for testing the part and should not be written to.

Addressing the On-Chip Registers

Writing

A write operation to the AD7851 consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which regis-

ter is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are written that

the data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the overall

write register hierarchy.

Table I. Write Register Addressing

ADDR1 ADDR0 Comment

00This combination does not address any register so the subsequent 14 data bits are ignored.

01This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test register.

10This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written

to the selected calibration register.

11This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the

control register.

Reading

To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These

bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address

bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be

from the ADC output data register.

Once the read selection bits are set in the control register, all subsequent read operations that follow will be from the selected register

until the read selection bits are changed in the control register.

Table II. Read Register Addressing

RDSLT1 RDSLT0 Comment

00All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up default

setting. There will always be two leading zeros when reading from the ADC output data register.

01All successive read operations will be from TEST REGISTER.

10All successive read operations will be from CALIBRATION REGISTERS.

11All successive read operations will be from STATUS REGISTER.

ADDR1, ADDR0

DECODE

TEST

CONTROL

GAIN (1)

OFFSET (1)

DAC (8)

GAIN (1)

OFFSET (1)

OFFSET (1) GAIN (1)

01 10 11

00 01 10 11

CALSLT1, CALSLT0

DECODE

CALIBRATION

REGISTERS

Figure 4. Write Register Hierarchy/Address Decoding

RDSLT1, RDSLT0

DECODE

TEST

CALIBRATION

REGISTERS

STATUS

GAIN (1)

OFFSET (1)

DAC (8)

GAIN (1)

OFFSET (1)

OFFSET (1) GAIN (1)

01 10 11

00 01 10 11

CALSLT1, CALSLT0

DECODE

ADC OUTPUT

DATA REGISTER

Figure 5. Read Register Hierarchy/Address Decoding

–11–

REV. B

AD7851

CONTROL REGISTER

The arrangement of the control register is shown below. The control register is a write-only register and contains 14 bits of data. The

control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described

below. The power-up status of all bits is 0.

MSB

ZERO ZERO ZERO ZERO PMGT1 PMGT0 RDSLT1

RDSLT0

2/3 MODE

CONVST CALMD CALSLT1 CALSLT0 STCAL

LSB

Control Register Bit Function Descriptions

Bit No. Mnemonic Comment

13 ZERO These four bits must be set to 0 when writing to the control register.

12 ZERO

11 ZERO

10 ZERO

9PMGT1 Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various

8PMGT0 power-down modes (see Power-Down section for more details).

7 RDSLT1 Theses two bits determine which register is addressed for the read operations. See Table II.

6 RDSLT0

52/3 MODE Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,

Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by

default after every read cycle; thus when using Interface Mode 1, this bit needs to be set to 1 in every

write cycle.

4 CONVST Conversion Start Bit. A Logic 1 in this bit position starts a single conversion, and this bit is automati-

cally reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration

(see Calibration section).

3 CALMD Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III).

2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions:

1 CALSLT0 With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per-

0 STCAL formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration.

With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration

Table III. Calibration Selection

CALMD CALSLT1 CALSLT0 Calibration Type

00 0 A full internal calibration is initiated where the internal DAC is calibrated followed by the

internal gain error, and finally the internal offset error is calibrated out. This is the default setting.

00 1 Here the internal gain error is calibrated out followed by the internal offset error calibrated

out.

01 0This calibrates out the internal offset error only.

01 1This calibrates out the internal gain error only.

10 0 A full system calibration is initiated here where first the internal DAC is calibrated, fol-

lowed by the system gain error, and finally the system offset error is calibrated out.

10 1Here the system gain error is calibrated out followed by the system offset error.

11 0This calibrates out the system offset error only.

11 1This calibrates out the system gain error only.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

AD7851KNZ

Mfr. #:

Buy AD7851KNZ

Manufacturer:

Description:

Analog to Digital Converters - ADC 14B 333kSPS Serial Sampling

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD7851KNZ

AD7851KNZ

Products related to this Datasheet