–21–
REV. B
AD7851
Table VII. Power Consumption vs. Throughput
Throughput Rate Power AD7851
1 kSPS 9 mW
2 kSPS 18 mW
THROUGHPUT RATE
(
Hz
)
100
10
0.01
0 2000200
1
400 600 800 1000 1200 1400 1600 1800
0.1
POWER (mW)
Figure 26. Power vs. Throughput AD7851
NOTE
When setting the power-down mode by writing to the part,
operating in an interface mode other than Interface Modes 4
and 5 is recommended. This way the user has more control to
initiate power-down and power-up commands.
CALIBRATION SECTION
Calibration Overview
The automatic calibration that is performed on power-up ensures
that the calibration options covered in this section will not be
required for a significant number of applications. The user will
not have to initiate a calibration unless the operating conditions
change (CLKIN frequency, analog input mode, reference voltage,
temperature, and supply voltages). The AD7851 has a number of
calibration features that may be required in some applications,
and there are a number of advantages in performing these differ-
ent types of calibration. First, the internal errors in the ADC can
be reduced significantly to give superior dc performance; and
second, system offset and gain errors can be removed. This allows
the user to remove reference errors (whether internal or external
references) and to make use of the full dynamic range of the
AD7851 by adjusting the analog input range of the part for a
specific system.
The AD7851 has two main calibration modes: self-calibration
and system calibration. There are various options in both self-
calibration and system calibration as outlined previously in
Table III. All the calibration functions can be initiated by puls-
ing the CAL pin or by writing to the control register and setting
the STCAL bit to 1. The timing diagrams that follow involve
using the CAL pin.
The duration of each of the different types of calibrations is
given in Table VIII for the AD7851 with a 6 MHz/7 MHz mas-
ter clock. These calibration times are master-clock dependent.
Table VIII. Calibration Times (AD7851 with 6 MHz CLKIN)
Type of Self- or System Calibration Time (ms)
Full 41.7
Gain + Offset 9.26
Offset 4.63
Gain 4.63
Automatic Calibration on Power-On
The CAL pin has a 0.15 µA pull-up current source connected to it
internally to allow for an automatic full self-calibration on power-
on. A full self-calibration will be initiated on power-on if a 10 nF
capacitor is connected from the CAL pin to DGND. The internal
current source connected to the CAL pin charges up the external
capacitor and the time required to charge the external capacitor
will depend on the size of the capacitor itself. This time should be
large enough to ensure that the internal reference is settled before
the calibration is performed. However, if an external reference is
being used, this reference must have stabilized before the auto-
matic calibration is initiated (a larger capacitor on the CAL pin
should be used if the external reference has not settled when the
autocalibration is initiated). Once the capacitor on the CAL pin
has charged, the calibration will be performed and will take 32 ms
(4 MHz CLKIN). Therefore, the autocalibration should be com-
plete before operating the part. After calibration, the part is accu-
rate to the 12-bit level and the specifications quoted on the data
sheet apply. There will be no need to perform another calibra-
tion unless the operating conditions change or unless a system
calibration is required.
Self-Calibration Description
There are a four different calibration options within the self-
calibration mode. There is a full self-calibration where the
DAC, internal offset, and internal gain errors are calibrated
out; there is (Gain + Offset) self-calibration which calibrates
out the internal gain error and then the internal offset errors
(the internal DAC is not calibrated here); and finally, there are
self-offset and self-gain calibrations that calibrate out the inter-
nal offset errors and the internal gain errors, respectively.
The internal capacitor DAC is calibrated by trimming each of the
capacitors in the DAC. It is the ratio of these capacitors to each
other that is critical, and so the calibration algorithm ensures
that this ratio is at a specific value by the end of the calibration
routine. For the offset and gain there are two separate capaci-
tors, one of which is trimmed when an offset or gain calibration
is performed. Again, it is the ratio of these capacitors to the
capacitors in the DAC that is critical and the calibration algo-
rithm ensures that this ratio is at a specified value for both
the offset and gain calibrations.
In bipolar mode, the midscale error is adjusted for an offset cali-
bration and the positive full-scale error is adjusted for the gain
calibration; in unipolar mode, the zero-scale error is adjusted for
an offset calibration and the positive full-scale error is adjusted
for a gain calibration.
AD7851
–22–
REV. B
SYSTEM OFFSET
CALIBRATION
SYS OFFSET
V
REF
– 1LSB
AGND
MAX SYSTEM OFFSET
IS ±5% OF V
REF
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V
REF
ANALOG
INPUT
RANGE
V
REF
– 1LSB
ANALOG
INPUT
RANGE
SYS OFFSET
AGND
MAX SYSTEM OFFSET
IS ±5% OF V
REF
V
REF
+ SYS OFFSET
Figure 28. System Offset Calibration
Figure 29 shows a system gain calibration (assuming a system
full scale greater than the reference voltage) where the analog
input range has been increased after the system gain calibration
is completed. A system full-scale voltage less than the reference
voltage may also be accounted for a by a system gain calibration.
SYSTEM GAIN
CALIBRATION
V
REF
– 1LSB
AGND
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V
REF
ANALOG
INPUT
RANGE
V
REF
– 1LSB
ANALOG
INPUT
RANGE
AGND
SYS FULL S.SYS FULL S.
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V
REF
Figure 29. System Gain Calibration
Finally in Figure 30 both the system offset and gain are accounted
for by the system offset followed by a system gain calibration.
First the analog input range is shifted upwards by the positive
system offset and then the analog input range is adjusted at the
top end to account for the system full scale.
SYSTEM OFFSET
CALIBRATION
FOLLOWED BY
SYSTEM GAIN
CALIBRATION
SYS OFFSET
V
REF
– 1LSB
AGND
MAX SYSTEM OFFSET
IS ±5% OF V
REF
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V
REF
ANALOG
INPUT
RANGE
V
REF
– 1LSB
ANALOG
INPUT
RANGE
SYS OFFSET
AGND
MAX SYSTEM OFFSET
IS ±5% OF V
REF
V
REF
+ SYS OFFSET
SYS F.S.
MAX SYSTEM FULL SCALE
IS ±2.5% FROM V
REF
SYS F.S.
Figure 30. System (Gain + Offset) Calibration
Self-Calibration Timing
Figure 27 shows the timing for a full self-calibration. Here the
BUSY line stays high for the full length of the self-calibration. A
self-calibration is initiated by bringing the CAL pin low (which
initiates an internal reset) and then high again or by writing to
the control register and setting the STCAL bit to 1 (note that if
the part is in a power-down mode, the CAL pulse width must
take account of the power-up time). The BUSY line is triggered
high from the rising edge of CAL (or the end of the write to the
control register if calibration is initiated in the software), and
BUSY will go low when the full self-calibration is complete after
a time t
CAL
.
t
1
= 100ns MIN,
t
15
= 2.5 t
CLKIN
MAX,
t
CAL
= 250026 t
CLKIN
CAL (I/P)
BUSY (O/P)
t
1
t
15
t
CAL
Figure 27. Timing Diagram for Full Self-Calibration
For the self-(gain + offset), self-offset, and self-gain calibrations,
the BUSY line will be triggered high by the rising edge of the
CAL signal (or the end of the write to the control register if cali-
bration is initiated in the software) and will stay high for the full
duration of the self-calibration. The length of time that the BUSY
is high will depend on the type of self-calibration that is initiated.
Typical figures are given in Table VIII. The timing diagrams for
the other self-calibration options will be similar to Figure 27.
System Calibration Description
System calibration allows the user to take out system errors
external to the AD7851 as well as calibrate the errors of the
AD7851 itself. The maximum calibration range for the system
offset errors is ±5% of V
REF
and for the system gain errors is
±2.5% of V
REF
. This means that the maximum allowable system
offset voltage applied between the AIN(+) and AIN(–) pins for
the calibration to adjust out this error is ±0.05 × V
REF
(that is,
the AIN(+) can be 0.05 × V
REF
above AIN(–) or 0.05 × V
REF
below AIN(–)). For the system gain error, the maximum allow-
able system full-scale voltage, in unipolar mode, that can be
applied between AIN(+) and AIN(–) for the calibration to
adjust out this error is V
REF
± 0.025 × V
REF
(that is, the AIN(+)
can be V
REF
+ 0.025 × V
REF
above AIN(–) or V
REF
– 0.025 ×
V
REF
above AIN(–)). If the system offset or system gain errors
are outside the ranges mentioned, the system calibration algo-
rithm will reduce the errors as much as the trim range allows.
Figures 28, 29, and 30 illustrate why a specific type of system
calibration might be used. Figure 28 shows a system offset
calibration (assuming a positive offset) where the analog input
range has been shifted upwards by the system offset after the
system offset calibration is completed. A negative offset may
also be accounted for by a system offset calibration.
–23–
REV. B
AD7851
System Gain and Offset Interaction
The inherent architecture of the AD7851 leads to an interaction
between the system offset and gain errors when a system calibra-
tion is performed. Therefore, it is recommended to perform the
cycle of a system offset calibration followed by a system gain cali-
bration twice. Separate system offset and system gain calibrations
reduce the offset and gain errors to at least the 14-bit level. By
performing a system offset calibration first and a system gain
calibration second, priority is given to reducing the gain error to
zero before reducing the offset error to zero. If the system errors
are small, a system offset calibration would be performed, fol-
lowed by a system gain calibration. If the systems errors are
large (close to the specified limits of the calibration range), this
cycle would be repeated twice to ensure that the offset and gain
errors were reduced to at least the 14-bit level. The advantage of
doing separate system offset and system gain calibrations is that
the user has more control over when the analog inputs need to
be at the required levels, and the CONVST signal does not have
to be used.
Alternatively, a system (gain + offset) calibration can be per-
formed. It is recommended to perform three system (gain +
offset) calibrations to reduce the offset and gain errors to the
14-bit level. For the system (gain + offset) calibration priority
is given to reducing the offset error to 0 before reducing the
gain error to 0. Thus, if the system errors are small then two
system (gain + offset) calibrations will be sufficient. If the
system errors are large (close to the specified limits of the
calibration range), three system (gain + offset) calibrations
may be required to reduce the offset and gain errors to at
least the 14-bit level. There will never be any need to perform
more than three system (offset + gain) calibrations.
In bipolar mode, the midscale error is adjusted for an offset cali-
bration and the positive full-scale error is adjusted for the gain
calibration; in unipolar mode, the zero-scale error is adjusted for
an offset calibration and the positive full-scale error is adjusted
for a gain calibration.
System Calibration Timing
The calibration timing diagram in Figure 31 is for a full system
calibration where the falling edge of CAL initiates an internal
reset before starting a calibration (note that if the part is in power-
down mode the CAL pulse width must take account of the power-up
time). If a full system calibration is performed in the software, it
is easier to perform separate gain and offset calibrations so
that the CONVST bit in the control register does not have to be
programmed in the middle of the system calibration sequence.
The rising edge of CAL starts calibration of the internal DAC
and causes the BUSY line to go high. If the control register is
set for a full system calibration, the CONVST must be used
also. The full-scale system voltage should be applied to the ana-
log input pins from the start of calibration. The BUSY line will
go low once the DAC and system gain calibration are complete.
Next, the system offset voltage is applied to the AIN pin for a
minimum setup time (t
SETUP
) of 100 ns before the rising edge of
the CONVST and remains until the BUSY signal goes low. The
rising edge of the CONVST starts the system offset calibration
section of the full system calibration and also causes the BUSY
signal to go high. The BUSY signal will go low after a time t
CAL2
when the calibration sequence is complete.
The timing for a system (gain + offset) calibration is very similar
to that of Figure 31, the only difference being that the time
t
CAL1
will be replaced by a shorter time of the order of t
CAL2
as
the internal DAC will not be calibrated. The BUSY signal will
signify when the gain calibration is finished and when the part is
ready for the offset calibration.
CONVST (I/P)
AIN (I/P)
t
16
t
SETUP
CAL (I/P)
BUSY (O/P)
t
1
t
15
t
CAL1
t
CAL2
V
SYSTEM FULL SCALE
V
OFFSET
t
1
= 100ns MIN,
t
14
= 50 MAX,
t
15
= 4
t
CLKIN
MAX,
t
CAL1
= 222228
t
CLKIN
MAX,
t
CAL2
= 27798
t
CLKIN
Figure 31. Timing Diagram for Full System Calibration
The timing diagram for a system offset or system gain calibration is
shown in Figure 32. Here again the CAL is pulsed and the rising
edge of the CAL initiates the calibration sequence (or the calibra-
tion can be initiated in software by writing to the control register).
The rising edge of the CAL causes the BUSY line to go high and it
will stay high until the calibration sequence is finished. The analog
input should be set at the correct level for a minimum setup time
(t
SETUP
) of 100 ns before the rising edge of CAL and stay at the
correct level until the BUSY signal goes low.
AIN (I/P)
t
SETUP
CAL (I/P)
BUSY (O/P)
t
15
t
CAL2
t
1
V
SYSTEM FULL SCALE
OR V
SYSTEM OFFSET
Figure 32. Timing Diagram for System Gain or System
Offset Calibration

AD7851KNZ

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Analog to Digital Converters - ADC 14B 333kSPS Serial Sampling
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