–5–
REV. B
AD7851
Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges are with the POLARITY pin HIGH. For the POLARITY pin
LOW, then the opposite edge of SCLK will apply.
Limit at T
MIN
, T
MAX
Parameter (A, K Versions) Unit Description
f
CLKIN
2
500 kHz min Master Clock Frequency
7 MHz max
f
SCLK
3
10 MHz max Interface Modes 1, 2, 3 (External Serial Clock)
f
CLK IN
MHz max Interface Modes 4, 5 (Internal Serial Clock)
t
1
4
100 ns min CONVST Pulse Width
t
2
50 ns max CONVST↓ to BUSY↑ Propagation Delay
t
CONVERT
3.25 µs max Conversion Time = 20 t
CLKIN
t
3
–0.4 t
SCLK
ns min SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
±0.4 t
SCLK
ns min/max SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)
t
4
0.6 t
SCLK
ns min SYNC↓ to SCLK↓ Setup Time, Interface Mode 4 Only
t
5
5
30 ns max Delay from SYNC↓ until DOUT Three-State Disabled
t
5A
5
30 ns max Delay from SYNC↓ until DIN Three-State Disabled
t
6
5
45 ns max Data Access Time after SCLK↓
t
7
30 ns min Data Setup Time prior to SCLK↑
t
8
20 ns min Data Valid to SCLK Hold Time
t
9
6
0.4 t
SCLK
ns min SCLK High Pulse Width (Interface Modes 4 and 5)
t
10
6
0.4 t
SCLK
ns min SCLK Low Pulse Width (Interface Modes 4 and 5)
t
11
30 ns min SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
30/0.4 t
SCLK
ns min/max (Continuous SCLK) Does Not Apply to Interface Mode 3
t
11A
50 ns max SCLK↑ to SYNC↑ Hold Time
t
12
7
50 ns max Delay from SYNC↑ until DOUT Three-State Enabled
t
13
90 ns max Delay from SCLK↑ to DIN Being Configured as Output
t
14
8
50 ns max Delay from SCLK↑ to DIN Being Configured as Input
t
15
2.5 t
CLKIN
ns max CAL↑ to BUSY↑ Delay
t
16
2.5 t
CLKIN
ns max CONVST↓ to BUSY↑ Delay in Calibration Sequence
t
CAL
9
41.7 ms typ Full Self-Calibration Time, Master Clock Dependent
(250026 t
CLKIN
)
t
CAL1
9
37.04 ms typ Internal DAC Plus System Full-Scale Calibration Time, Master Clock
Dependent (222228 t
CLKIN
)
t
CAL2
9
4.63 ms typ System Offset Calibration Time, Master Clock Dependent
(27798 t
CLKIN
)
t
DELAY
65 ns max Delay from CLK to SCLK
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V. See
Table X and timing diagrams for different interface modes and calibration.
2
Mark/space ratio for the master clock input is 40/60 to 60/40.
3
For Interface Modes 1, 2, 3, the SCLK maximum frequency will be 10 MHz. For Interface Modes 4 and 5, the SCLK will be an output and the frequency will be f
CLKIN
.
4
The CONVST pulse width will only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power-
Down section).
5
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
6
For self-clocking mode (Interface Modes 4, 5), the nominal SCLK high and low times will be 0.5 t
SCLK
= 0.5 t
CLKIN
.
7
The time t
12
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that t
12
as quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
8
The time t
14
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true
delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed , the user can drive the DIN line knowing
that a bus conflict will not occur.
9
The typical time specified for the calibration times is for a master clock of 6 MHz.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1
(AV
DD
= DV
DD
= 5.0 V ⴞ 5%; f
CLKIN
= 6 MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
