AD7851
–6–
REV. B
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in
Interface Modes 2 and 3. To attain the maximum sample rate of
285 kHz in Interface Modes 2 and 3, reading and writing must
be performed during conversion. Figure 3 shows the timing dia-
gram for Interface Modes 4 and 5 with sample rate of 285 kHz.
At least a 330 ns acquisition time must be allowed (the time
from the falling edge of BUSY to the next rising edge of
CONVST) before the next conversion begins to ensure that the
part is settled to the 14-bit level. If the user does not want to
provide the CONVST signal, the conversion can be initiated in
software by writing to the control register.
1.6mA
2.1V
200µA
C
L
50pF
TO
OUTPUT
PIN
I
OL
I
OH
Figure 1. Load Circuit for Digital Output Timing
Specifications
DB15 DB0
DB11
POLARITY PIN LOGIC HIGH
SYNC (I/P)
SCLK (I/P)
t
3
BUSY (O/P)
CONVST (I/P)
t
2
t
5
t
11
t
6
t
9
t
10
15
6
16
t
12
DOUT (O/P)
DB0DB11
t
8
DIN (I/P)
THREE-STATE
THREE-STATE
DB15
t
CONVERT
t
CONVERT
= 3.25µs MAX, t
1
= 100ns MIN,
t
5
= 30ns MAX, t
7
= 30ns MIN
t
1
t
6
t
7
Figure 2. Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
POLARITY PIN LOGIC HIGH
SYNC (O/P)
SCLK (O/P)
t
4
BUSY (O/P)
CONVST (I/P)
t
2
t
5
t
11
t
12
t
9
t
10
15
6
16
DOUT (O/P)
DB0DB11
t
8
DIN (I/P)
DB15 DB0
THREE-STATE
DB11
THREE-STATE
DB15
t
CONVERT
t
CONVERT
= 3.25µs MAX, t
1
= 100ns MIN,
t
5
= 30ns MAX, t
7
= 30ns MIN
t
1
t
6
t
7
Figure 3. Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)
–7–
REV. B
AD7851
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C, unless otherwise noted.)
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DV
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AV
DD
to DV
DD
. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . . –0.3 V to AV
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DV
DD
+ 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DV
DD
+ 0.3 V
REF
IN
/REF
OUT
to AGND . . . . . . . . . . –0.3 V to AV
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
2
. . . . . . . . . ±10 mA
Operating Temperature Range
Commercial (A, K Versions) . . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
PDIP Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . .34.7°C/W
Lead Temperature, (Soldering, 10 secs) . . . . . . . . . . 260°C
SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . 75°C/W (SOIC), 122.28°C/W (SSOP)
θ
JC
Thermal Impedance . . . 25°C/W (SOIC), 31.25°C/W (SSOP)
PINOUT FOR DIP, SOIC, AND SSOP
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
AD7851
TOP VIEW
(Not to Scale)
CONVST
BUSY
SLEEP
REF
IN
/REF
OUT
AV
DD
AGND
C
REF
1
C
REF
2
AIN(+)
AIN(–)
NC
AGND
SYNC
SCLK
CLKIN
DIN
DOUT
DGND
DV
DD
CAL
SM2
SM1
POLARITY
AMODE
NC = NO CONNECT
ORDERING GUIDE
1
Linearity
Temperature Error Throughput Throughput Package
Model Range (LSB)
2
Rate (kSPS) at 125C (kSPS) Description Options
3
AD7851AN –40°C to +85°C ±2 333 238 PDIP N-24
AD7851KN 0°C to 85°C ±1 285 238 PDIP N-24
AD7851AR –40°C to +85°C ±2 333 238 SOIC R-24
AD7851AR-REEL –40°C to +85°C ±2 333 238 SOIC R-24
AD7851ARZ
3
–40°C to +85°C ±2 333 238 SOIC R-24
AD7851ARZ-REEL
3
–40°C to +85°C ±2 333 238 SOIC R-24
AD7851KR 0°C to 85°C ± 1 285 238 SOIC R-24
AD7851KR-REEL 0°C to 85°C ±1 285 238 SOIC R-24
AD7851KRZ
3
0°C to 85°C ±1 285 238 SOIC R-24
AD7851KRZ-REEL
3
0°C to 85°C ±1 285 238 SOIC R-24
AD7851ARS –40°C to +85°C ±2 333 238 SSOP RS-24
AD7851ARS-REEL –40°C to +85°C ±2 333 238 SSOP RS-24
EVAL-AD7851CB
4
Evaluation Board
EVAL-CONTROL BRD2
5
Controller Board
NOTES
1
Both A and K Grades are guaranteed up to 125°C, but at a lower throughput of 238 kHz (5 MHz).
2
Linearity error refers to the integral linearity error.
3
Z = Pb-free part.
4
This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.
5
This board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. To order a
complete evaluation kit, the particular ADC evaluation board needs to be ordered, e.g., EVAL-AD7851CB, the EVAL-CONTROL BRD2, and a 12 V ac trans-
former. See the Evaluation Board application note for more information.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7851 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5 kV
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
AD7851
–8–
REV. B
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total Unadjusted Error
This is the deviation of the actual code from the ideal code tak-
ing all errors into account (gain, offset, integral nonlinearity, and
other errors) at any point along the transfer function.
Unipolar Offset Error
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB)
when operating in unipolar mode.
Positive Full-Scale Error
This applies to unipolar and bipolar modes and is the deviation of
the last code transition from the ideal AIN(+) voltage (AIN(–) +
full scale – 1.5 LSB) after the offset error has been adjusted out.
Negative Full-Scale Error
This applies to bipolar mode only and is the deviation of the
first code transition (10 . . . 000 to 10 . . . 001) from the ideal
AIN(+) voltage (AIN(–) – V
REF
/2 + 0.5 LSB).
Bipolar Zero Error
This is the deviation of the midscale transition (all 1s to all 0s)
from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB).
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode at the end
of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (f
S
/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitiza-
tion process; the more levels, the smaller the quantization noise.
The theoretical signal-to-(noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N +1.76)dB
Thus, for a 14-bit converter, this is 86 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7851, it is defined as
THD
VVVVV
V
(d ) 20logB =
++++
()
2
2
3
2
4
2
5
2
6
2
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
, and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second-order terms include (fa + fb) and (fa – fb), while the
third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and
(fa – 2fb).
Testing is performed using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second-order terms are usually distanced
in frequency from the original sine waves while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.
Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in ADC output at fre-
quency f to the power of the full-scale sine wave applied to the
supply voltage (V
DD
). The units are in LSB, % of FS per % of
supply voltage, or expressed logarithmically, in dB (PSRR (dB)
= 10 log (Pf/Pfs)).
Full Power Bandwidth (FPBW)
FPBW is that frequency at which the amplitude of the recon-
structed fundamental (using FFTs and neglecting harmonics
and SNR) is reduced by 3 dB for a full-scale input.

AD7851KNZ

Mfr. #:
Manufacturer:
Description:
Analog to Digital Converters - ADC 14B 333kSPS Serial Sampling
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