ADT7466
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THEORY OF OPERATION
SERIAL BUS INTERFACE
The serial system management bus (SMBus) is used to control
the ADT7466. The ADT7466 is connected to this bus as a slave
device under the control of a master controller.
The ADT7466 has an SMBus timeout feature. When this is
enabled, the SMBus times out after typically 25 ms of no
activity. However, this feature is enabled by default. Bit 5 of
Configuration Register 1 (0x00) should be set to 1 to disable
this feature.
The ADT7466 supports optional packet error checking (PEC).
It is triggered by supplying the extra clock pulses for the PEC
byte. The PEC byte is calculated using CRC-8. The frame check
sequence (FCS) conforms to CRC-8 by the polynomial
()
1128 +++=
C
Consult the SMBus Specifications Rev. 1.1 for more information
(www.smbus.org).
The ADT7466 has a 7-bit serial bus address, which is fixed at
1001100.
The serial bus protocol operates as follows:
The master initiates data transfer by establishing a start condition,
defined as a high-to-low transition on the serial data line SDA
while the serial clock line SCL remains high. This indicates that
an address/data stream follows. All slave peripherals connected
to the serial bus respond to the start condition, and shift in the
next 8 bits, consisting of a 7-bit address (MSB first) and a R/
W
bit, which determines the direction of the data transfer, that is,
whether data is written to or read from the slave device.
The address of the ADT7466 is set at 1001100. Since the address
must always be followed by a write bit (0) or a read bit (1), and
data is generally handled in 8-bit bytes, it may be more conven-
ient to think that the ADT7466 has an 8-bit write address of
10011000 (0x98) and an 8-bit read address of 10011001 (0x99).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the 9th clock pulse, known as the acknowledge
bit. All other devices on the bus now remain idle while the
selected device waits for data to be read from or written to it. If
the R/
W
bit is 0, the master writes to the slave device. If the
R/
W
bit is 1, the master reads from the slave device.
Data is sent over the serial bus in sequences of 9 clock pulses,
8 bits of data followed by an acknowledge bit from the slave
device. Transitions on the data line must occur during the low
period of the clock signal and remain stable during the high
period, because a low-to-high transition when the clock is high
may be interpreted as a stop signal. The number of data bytes
that can be transmitted over the serial bus in a single read or
write operation is limited only by what the master and slave
devices can handle.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device overrides the acknowledge bit by
pulling the data line high during the low period before the
ninth clock pulse. This is known as No Acknowledge. The
master takes the data line low during the low period before the
10th clock pulse, and then high during the 10th clock pulse to
assert a stop condition.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and subsequently cannot be changed without
starting a new operation.
ADT7466 write operations contain either one or two bytes, and
read operations contain one byte, and perform the following
functions.
To write data to one of the device data registers or read data
from it, the address pointer register must be set so that the
correct data register is addressed, and data can be written to
that register or read from it. The first byte of a write operation
always contains an address that is stored in the address pointer
register. If data is to be written to the device, the write operation
contains a second data byte that is written to the register
selected by the address pointer register. This is shown in
Figure 17. The device address is sent over the bus followed by
R/
W
set to 0. This is followed by two data bytes. The first data
byte is the address of the internal data register to be written to,
which is stored in the address pointer register. The second data
byte is the data to be written to the internal data register.
When reading data from a register, there are two possibilities.
If the ADT7466 address pointer register value is unknown or
not the desired value, it is necessary to first set it to the correct
value before data can be read from the desired data register.
This is done by performing a write to the ADT7466 as before,
but only the data byte containing the register address is sent
since data is not to be written to the register. This is shown in
Figure 18.
A read operation is then performed consisting of the serial bus
address, R/
W
bit set to 1, followed by the data byte read from
the data register. This is shown in Figure 19.
