ADT7466
Rev. 2 | Page 15 of 48 | www.onsemi.com
ALERT RESPONSE ADDRESS (ARA)
ARA is a feature of SMBus devices that allows an interrupting
device to identify itself to the host when multiple devices exist
on the same bus. The
ALERT
output can be used as an interrupt
output, or it can be used as an
ALERT
. One or more outputs can
be connected to a common
ALERT
line connected to the
master. If a device’s
ALERT
line goes low, the following occurs:
1.
ALERT
is pulled low.
2. The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address, which must not be used as a specific device
address.
3. The device whose
ALERT
output is low responds to the
alert response address, and the master reads its device
address. The address of the device is now known, and it
can be interrogated in the usual way.
4. If more than one device’s
ALERT
output is low, the one
with the lowest device address has priority, in accordance
with normal SMBus arbitration.
5. Once the ADT7466 responds to the alert response address,
the master must read the status registers, the
ALERT
is
cleared only if the error condition no longer exists.
SMBus TIMEOUT
The ADT7466 includes an SMBus timeout feature. If there is no
SMBus activity for 25 ms, the ADT7466 assumes that the bus is
locked, and it releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so they
are disabled.
Table 5. Configuration Register 1—Register 0x00
Bit Address and Value Description
<5> TODIS = 0 SMBus timeout enabled (default)
<5> TODIS = 1 SMBus timeout disabled
VOLTAGE MEASUREMENT
The ADT7466 has two external voltage measurement channels.
Pin 11 and Pin 12 are analog inputs with a range of 0 V to
2.25 V. It can also measure its own supply voltage, V
CC
. The V
CC
supply voltage measurement is carried out through the V
CC
pin
(Pin 6). Setting Bit 6 of Configuration Register 1 (0x00) allows a
5 V supply to power the ADT7466 and be measured without
overranging the V
CC
measurement channel.
A/D Converter
All analog inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter. This has a resolution
of 10 bits. The basic input range is 0 V to 2.25 V, but the V
CC
input has built in attenuators to allow measurement of 3.3 V or
5 V. To allow for the tolerance of the supply voltage, the ADC
produces an output of 3/4 full scale (decimal 768 or 0x300) for
the nominal supply voltage, and so has adequate headroom to
cope with overvoltages.
Table 9 shows the input ranges of the analog inputs and the
output codes of the ADC.
Table 6. Voltage Measurement Registers
Register Description Default
0x0A AIN1 reading 0x00
0x0B AIN2 reading 0x00
0x0C V
CC
reading 0x00
Associated with each voltage measurement channel are high
and low limit registers. Exceeding the programmed high or low
limit causes the appropriate status bit to be set. Exceeding either
limit can also generate
ALERT
interrupts.
Table 7. Voltage Measurement Limit Registers
Register Description Default
0x14 AIN1 low limit 0x00
0x15 AIN1 high limit 0xFF
0x16 AIN2 low limit 0x00
0x17 AIN2 high limit 0xFF
0x18 V
CC
low limit 0x00
0x19 V
CC
high limit 0xFF
When the ADC is running, it samples and converts a voltage
input in 1 ms, and averages 16 conversions to reduce noise.
Therefore a measurement on each input takes nominally 16 ms.
Turn Off Averaging
For each voltage measurement read from a value register, 16
readings have actually been made internally and the results
averaged, before being placed into the value register. There can
be an instance where faster conversions are required. Setting
Bit 4 of Configuration Register 2 (0x01) turns averaging off.
This effectively gives a reading 16 times faster (1 ms), but as a
result the reading can be noisier.
Single-Channel ADC Conversions
Setting Bit 3 of Configuration Register 4 (0x03) places the
ADT7466 into single-channel ADC conversion mode. In this
mode, the ADT7466 can be made to read a single voltage channel
only. If the internal ADT7466 clock is used, the selected input is
read every 1 ms. The appropriate ADC channel is selected by
writing to Bits 2:0 of Configuration Register 4 (0x03).
