ADT7466
Rev. 2 | Page 23 of 48 | www.onsemi.com
16-Bit Limits
The fan tach measurements are 16-bit results. The fan tach
limits are also 16 bits, consisting of a high byte and low byte.
Since fans running under speed or stalled are normally the only
conditions of interest, only high limits exist for fan tachs. Since
the fan tach period is actually being measured, exceeding the
limit indicates a slow or stalled fan.
Table 19. Fan Limit Registers
Register Description Default
0x4C TACH1 minimum low byte 0xFF
0x4D TACH1 minimum high byte 0xFF
0x4E TACH2 minimum low byte 0xFF
0x4F TACH2 minimum high byte 0xFF
Out-of-Limit Comparisons
Once all limits have been programmed, ADT7466 monitoring
can be enabled. The ADT7466 measures all parameters in round-
robin format and sets the appropriate status bit for out-of-limit
conditions. Comparisons are done differently depending on
whether the measured value is being compared to a high or low
limit.
A greater than comparison is performed when comparing with
the high limit.
A less than or equal to comparison is performed when comparing
with the low limit.
Status Registers
The results of limit comparisons are stored in Status Register 1
and Status Register 2. The status register bit for each channel
reflects the status of the last measurement and limit comparison
on that channel. If a measurement is within limits, the corre-
sponding status register bit is cleared to 0. If the measurement is
out-of-limits the corresponding status register bit is set to 1.
The state of the various measurement channels can be polled by
reading the status registers over the serial bus. When Bit 7
(OOL) of Status Register 1 (0x10) is 1, an out-of-limit event has
been flagged in Status Register 2. Therefore the user need only
read Status Register 2 when this bit is set. Alternatively, the
ALERT
output (Pin 14) can be used as an interrupt, which
automatically notifies the system supervisor of an out-of-limit
condition. Reading the status registers clears the appropriate
status bit as long as the error condition that caused the interrupt
has cleared. Status register bits are sticky, meaning that they
remain set until read by software. Whenever a status bit is set,
indicating an out-of-limit condition, it remains set even if the
event that caused it cleared (until read). The only way to clear
the status bit is to read the status register when the event clears.
Interrupt status mask registers (0x12, 0x13) allow individual
interrupt sources to be masked from causing an
ALERT
.
However, if one of these masked interrupt sources goes out-of-
limit, its associated status bit is set in the interrupt status
registers.
Table 20. Interrupt Status Register 1 (Reg. 0x10)
Bit No. Name Description
7 OOL 1 indicates that a bit in Status Register 2 is set
and that Status Register 2 should be read.
6 AIN1 1 indicates that AIN1 is out of limit.
5 AIN2 1 indicates that AIN2 is out of limit.
4 VCC 1 indicates that V
CC
is out of limit.
3 REM 1 indicates that the remote temperature
measurement is out of limit.
2 LOC 1 indicates that the local temperature
measurement is out of limit.
1 FAN1 1 indicates that the Tach 1 count is above
limit (fan speed below limit).
0 FAN2 1 indicates that the Tach 2 count is above
limit (fan speed below limit).
Table 21. Interrupt Status Register 2 (Reg. 0x11)
Bit No. Name Description
5 THRM2 1 indicates that TH1 is open-circuit.
4 THRM1 1 indicates that TH2 is open-circuit.
3 D2 1 indicates that Remote Temperature
Sensing Diode 2 is open-circuit or short-
circuit.
2 D1 1 indicates that Remote Temperature
Sensing Diode 1 is open-circuit or short-
circuit.
1 PHOT 1 indicates that the
PROCHOT
limit has been
exceeded.
0 OVT 1 indicates that a
THERM
overtemperature
limit has been exceeded.
ALERT INTERRUPT BEHAVIOR
The ADT7466 can be polled for status, or an
ALERT
interrupt
can be generated for out-of-limit conditions. It is important to
note how the
ALERT
output and status bits behave when
writing interrupt handler software.
04711-027
HIGH LIMIT
TEMPERATURE
STICKY
STATUS
BIT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
CLEARED ON READ
(TEMP BELOW LIMIT)
ALERT
Figure 28. ALERT
and Status Bit Behavior
Figure 28 shows how the
ALERT
output and sticky status bits
behave. Once a limit is exceeded, the corresponding status bit is
