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MT4LSDT464HG-133G4

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
32MB, 64MB, 128MB (x64, SR)
144-PIN SDRAM SODIMM
09005aef80748a77 Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
19 ©2004 Micron Technology, Inc. All rights reserved.
NOTE:
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge
of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write sequence to the end of the
EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
Table 18: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION SYMBOL MIN MAX UNITS
SUPPLY VOLTAGE
V
DD 33.6 V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH VDD x 0.7 VDD + 0.5 V
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL -1 VDD x 0.3 V
OUTPUT LOW VOLTAGE: I
OUT = 3mA
V
OL –0.4 V
INPUT LEAKAGE CURRENT: V
IN = GND to VDD
ILI –10 µA
OUTPUT LEAKAGE CURRENT: V
OUT = GND to VDD
ILO –10 µA
STANDBY CURRENT:
SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V ±10%
I
SB –30 µA
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
I
CC –2 mA
Table 19: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start
t
BUF 1.3 µs
Data-out hold time
t
DH 200 ns
SDA and SCL fall time
t
F 300 ns 2
Data-in hold time
t
HD:DAT 0 µs
Start condition hold time
t
HD:STA 0.6 µs
Clock HIGH period
t
HIGH 0.6 µs
Noise suppression time constant at SCL, SDA inputs
t
I50ns
Clock LOW period
t
LOW 1.3 µs
SDA and SCL rise time
t
R0.3µs2
SCL clock frequency
f
SCL 400 KHz
Data-in setup time
t
SU:DAT 100 ns
Start condition setup time
t
SU:STA 0.6 µs 3
Stop condition setup time
t
SU:STO 0.6 µs
WRITE cycle time
t
WRC 10 ms 4
32MB, 64MB, 128MB (x64, SR)
144-PIN SDRAM SODIMM
09005aef80748a77 Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
20 ©2004 Micron Technology, Inc. All rights reserved.
Table 20: Serial Presence-Detect Matrix
“1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”; notes appear at end of Serial Presence-Detect Matrix
BYTE DESCRIPTION
ENTRY
(VERSION)
MT4LSDT464H MT4LSDT864H MT4LSDT1664H
0
Number of Bytes Used by Micron
128808080
1
Total Number of SPD Memory Bytes
256080808
2
Memory Type
SDRAM040404
3
Number of Row Addresses
12 or 13 0C 0C 0D
4
Number of Column Addresses
8 or 9080909
5
Number of Module Ranks
1 01 01 01
6
Module Data Width
64 40 40 40
7
Module Data Width (Continued)
0000000
8
Module Voltage Interface Levels
LVTTL010101
9
SDRAM Cycle Time,
t
CK (CAS Latency = 3)
7ns (-13E)
7.5ns (-133)
8ns (-10E)
70
75
80
70
75
80
70
75
80
10
SDRAM Access from CLK,
t
AC (CAS Latency = 3)
5.4ns (-13E/-133)
6ns (-10E)
54
60
54
60
54
60
11
Module Configuration Type
NONE 00 00 00
12
Refresh Rate/Type
15.6µs or
7.81µs/SELF
80 80 82
13
SDRAM Width (Primary SDRAM)
16 10 10 10
14
Error-checking SDRAM Data Width
00 00 00
15
Minimum Clock Delay from Back-to-Back
Random Column Addresses,
t
CCD
1010101
16
Burst Lengths Supported
1, 2, 4, 8, PAGE 8F 8F 8F
17
Number of Banks on SDRAM Device
4040404
18
CAS Latencies Supported
2, 306606
19
CS Latency
0010101
20
WE Latency
0010101
21
SDRAM Module Attributes
UNBUFFERED 00 00 00
22
SDRAM Device Attributes: General
0E 0E 0E 0E
23
SDRAM Cycle Time,
t
CK
(CAS Latency = 2) 10 (-133/-10E) A0
7.5ns (13E)
10ns (-133/-10E)
75
A0
75
A0
75
A0
24
SDRAM Access from CLK,
t
AC
(CAS Latency = 2)
54ns (-13E)
6ns (-133/-10E)
54
60
54
60
54
60
25
SDRAM Cycle Time,
t
CK
(CAS Latency = 1)
00 00 00
26
SDRAM Access from CLK,
t
AC
(CAS Latency = 1)
00 00 00
27
Minimum Row Precharge Time,
t
RP
15ns (-13E)
20ns (-133/-10E)
0F
14
0F
14
0F
14
28
Minimum Row Active to Row Active,
t
RRD
14ns (-13E)
15ns (-133)
20ns (-10E)
0E
0F
14
0E
0F
14
0E
0F
14
29
Minimum RAS# to CAS# Delay,
t
RCD
15ns (-13E)
20ns
(-133/-10E)
0F
14
0F
14
0F
14
32MB, 64MB, 128MB (x64, SR)
144-PIN SDRAM SODIMM
09005aef80748a77 Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
21 ©2004 Micron Technology, Inc. All rights reserved.
NOTE:
1. The value of
t
RAS used for -13E modules is calculated from
t
RC -
t
RP. Actual device spec. value is 37ns.
30
Minimum RAS# Pulse Width,
t
RAS (See note 1)
45ns (-13E)
44ns (133)
50ns (-10E)
2D
2C
32
2D
2C
32
2D
2C
32
31
Module Rank Density
32MB, 64MB,
or 128MB
08 10 20
32
Command and Address Setup Time,
t
AS,
t
CMS
1.5ns (-13E/-133)
2ns (-10E)
15
20
15
20
15
20
33
Command and Address Hold Time,
t
AH,
t
CMH
0.8ns (-13E/-133)
1ns (-10E)
08
10
08
10
08
10
34
Data Signal Input Setup Time,
t
DS
1.5ns (-13E/-133)
2ns (-10E)
15
20
15
20
15
20
35
Data Signal Input Hold Time,
t
DH
0.8ns (-13E/-133)
1ns (-10E)
08
10
08
10
08
10
36–
40
Reserved
00 00 00
41
Device Minimum Active/Auto-Refresh Time,
t
RC
66ns (-13E)
71ns (-133)
66ns (-10E)
3C
42
46
3C
42
46
3C
42
46
42–
61
Reserved
00 00 00
62
SPD Revision
REV. 2.0020202
63
Checksum For Bytes 0-62
(-13E)
(-133)
(-10E)
82
CE
1A
8B
D7
23
9E
EA
36
64
Manufacturer’s JEDEC ID Code
MICRON 2C 2C 2C
65-71
Manufacturer’s JEDEC ID Code (Cont.)
FF FF FF
72
Manufacturing Location
1 - 11 01 - 0B 01 - 0B 01 - 0B
73-90
Module Part Number (ASCII)
Variable Data Variable Data Variable Data
91
PCB Identification Code
1 - 9 01-09 01 - 09 01-09
92
Identification Code (Cont.)
0000000
93
Year of Manufacture in BCD
Variable Data Variable Data Variable Data
94
Week of Manufacture in BCD
Variable Data Variable Data Variable Data
95-98
Module Serial Number
Variable Data Variable Data Variable Data
99-125
Manufacturer-specific Data (RSVD)
Variable Data Variable Data Variable Data
126
System Frequency
100 MHz
(-13E/-133/-10E)
64 64 64
127
SDRAM Component & Clock Detail
8F 8F 8F
Table 20: Serial Presence-Detect Matrix (Continued)
“1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”; notes appear at end of Serial Presence-Detect Matrix
BYTE DESCRIPTION
ENTRY
(VERSION)
MT4LSDT464H MT4LSDT864H MT4LSDT1664H
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

MT4LSDT464HG-133G4

Mfr. #:
Buy MT4LSDT464HG-133G4
Manufacturer:
Micron
Description:
MODULE SDRAM 32MB 144SODIMM
Lifecycle:
New from this manufacturer.
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