MT4LSDT464HG-133G4 Datasheet MT4LSDT1664HG-133D1, MT4LSDT1664HG-13ED1, MT4LSDT1664HY-13EG1 | P4-P6

32MB, 64MB, 128MB (x64, SR)

144-PIN SDRAM SODIMM

09005aef80748a77 Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG.fm - Rev. C 6/04 EN

Table 5: Pin Descriptions

Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 more information

PIN NUMBERS SYMBOL TYPE DESCRIPTION

65, 66, 67 RAS#, CAS#, WE# Input

Command Inputs: RAS#, CAS#, and WE# (along with S#) define

the command being entered.

61 CK0 Input

Clock: CK is driven by the system clock. All SDRAM input

signals are sampled on the positive edge of CK. CK also

increments the internal burst counter and controls the output

registers.

62 CKE0 Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the

CK signal. Deactivating the clock provides PRECHARGE

POWER-DOWN and SELF REFRESH operation (all device banks

idle), ACTIVE POWER-DOWN (row ACTIVE in any device bank)

or CLOCK SUSPEND operation (burst access in progress). CKE is

synchronous except after the device enters power-down and

self refresh modes, where CKE becomes asynchronous until

after exiting the same mode. The input buffers, including CK,

are disabled during power-down and self refresh modes,

providing low standby power.

69 S0# Input

Chip Select: S# enables (registered LOW) and disables

(registered HIGH) the command decoder. All commands are

masked when S# is registered HIGH. S# is considered part of

the command code.

23, 24, 25, 26, 115, 116, 117,

118

DQMB0–DQMB7 Input

Input/Output Mask: DQMB is an input mask signal for write

accesses and an output enable signal for read accesses. Input

data is masked when DQMB is sampled HIGH during a WRITE

cycle. The output buffers are placed in a High-Z state (two-

clock latency) when DQMB is sampled HIGH during a READ

cycle.

106, 110 BA0, BA1 Input

Bank Address: BA0 and BA1 define to which device bank the

ACTIVE, READ, WRITE, or PRECHARGE command is being

applied.

29, 30, 31,32, 33, 34,

70 (128MB), 103, 104, 105,

109, 111, 112

A0–A11

(32MB, 64MB)

A0–A12

(128MB)

Input

Address Inputs: Provide the row address for ACTIVE

commands, and the column address and auto precharge bit

(A10) for READ/WRITE commands, to select one location out

of the memory array in the respective device bank. A10

sampled during a PRECHARGE command determines whether

the PRECHARGE applies to one device bank (A10 LOW, device

bank selected by BA0, BA1) or all device banks (A10 HIGH).

The address inputs also provide the op-code during a MODE

142 SCL Input

Serial Clock for Presence-Detect: SCL is used to synchronize the

presence-detect data transfer to and from the module.

141 SDA Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to

transfer addresses and data into and out of the presence-

detect portion of the module.

32MB, 64MB, 128MB (x64, SR)

144-PIN SDRAM SODIMM

09005aef80748a77 Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG.fm - Rev. C 6/04 EN

3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15,

16, 17, 18, 19, 20, 37, 38, 39,

40, 41, 43, 44, 47, 48, 49, 50,

51, 52, 53, 54, 83, 84, 85, 86,

87, 88, 89, 90, 93, 94, 95, 96,

97, 98, 99, 100, 121, 122, 123,

124, 125, 126, 127, 128, 131,

132, 133, 134, 135, 136, 137,

138

DQ0–DQ63 Input/

Output

Data I/O: Data bus.

11, 12, 27, 28, 45, 46, 63, 64,

81, 82, 101, 102, 113, 114, 129,

130, 143, 144

DD Supply

Power Supply: +3.3V ±0.3V.

1, 2, 21, 22, 35, 36, 55, 56, 75,

76, 91, 92, 107, 108, 119, 120,

139, 140

SS Supply

Ground.

70 (32MB, 64MB), 72, 73 NC –

Not Connected: These pins should be left unconnected.

57, 58, 59, 60, 68, 71, 74, 77,

78, 79, 80

DNU –

Do Not Use: These pins are not connected on these modules,

but are assigned pins on other modules in this product family.

Table 5: Pin Descriptions

Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 more information

PIN NUMBERS SYMBOL TYPE DESCRIPTION

32MB, 64MB, 128MB (x64, SR)

144-PIN SDRAM SODIMM

09005aef80748a77 Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG.fm - Rev. C 6/04 EN

Figure 3: Functional Block Diagram

SPD

SCL

SDA

A1 A2

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQMH

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQMB0

S0#

RAS#

CAS#

CKE0

WE#

CAS#: SDRAMs

CKE0: SDRAMs

WE#: SDRAMs

A0-A11: SDRAMs

A0-A12: SDRAMs

BA0-BA1: SDRAMs

A0-A11 (32MB, 64MB)

A0-A12 (128MB)

BA0-BA1

VDD

VSS

SDRAMs

U1, U2, U3, U4

DQML CS#

DQMB1

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQMH

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQMB4

DQML CS#

DQMB5

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQMH

DQ7

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQMB2

DQML CS#

DQMB3

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQMH

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQMB6

DQML CS#

DQMB7

CK0

RAS#: SDRAMs

10 pf

CK1

Standard modules use the following SDRAM devices

MT48LC4M16A2TG(IT) (32MB); MT48LC8M16A2TG(IT) (64MB);

MT48LC16M16A2TG(IT) (128MB)

Lead-free modules use the following SDRAM devices

MT48LC4M16A2P(IT) (32MB); MT48LC8M16A2P(IT) (64MB);

MT48LC16M16A2P(IT) (128MB)

Industrial Temperature modules use -75-speed components only.

NOTE:

1. All resistor values are 10Ω unless otherwise specified.

2. Per industry standard, Micron modules use various component speed

grades as referenced in the module part numbering guide at:

www.micron.com/support/numbering.html

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

MT4LSDT464HG-133G4

Mfr. #:

Buy MT4LSDT464HG-133G4

Manufacturer:

Micron

Description:

MODULE SDRAM 32MB 144SODIMM

Lifecycle:

New from this manufacturer.

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MT4LSDT464HG-133G4

MT4LSDT464HG-133G4

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