3&7#
AD8110/AD8111
–4–
TIMING CHARACTERISTICS (Parallel)
Limit
Parameter Symbol Min Max Unit
Data Setup Time t
1
20 ns
CLK Pulsewidth t
2
100 ns
Data Hold Time t
3
20 ns
CLK Pulse Separation t
4
100 ns
CLK to UPDATE Delay t
5
0ns
UPDATE Pulsewidth t
6
50 ns
Propagation Delay, UPDATE to Switch On or Off 8 ns
CLK, UPDATE Rise and Fall Times 100 ns
RESET Time 200 ns
t
5
t
6
t
4
t
2
t
1
t
3
1
0
1
0
1 = LATCHED
CLK
D0–D4
A0–A2
0 = TRANSPARENT
UPDATE
Figure 2. Timing Diagram, Parallel Mode
Table II. Logic Levels
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR
CLK, D0, D1, D2, CLK, D0, D1, D2, CLK, D0, D1, D2, CLK, D0, D1, D2,
D3, D4, A0, A1, A2 D3, D4, A0, A1, A2 D3, D4, A0, A1, A2 D3, D4, A0, A1, A2
CE, UPDATE CE, UPDATE DATA OUT DATA OUT CE, UPDATE CE, UPDATE DATA OUT DATA OUT
2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 μA max –400 μA min –400 μA max 3.0 mA min
3&7#
AD8110/AD8111
–5–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8110/AD8111 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 V
Internal Power Dissipation
2
AD8110/AD8111 80-Lead Plastic LQFP (ST) . . . . . 2.6 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
S
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air (T
A
= 25°C):
80-lead plastic LQFP (ST): θ
JA
= 48°C/W.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8110/AD8111 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure.
While the AD8110/AD8111 is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junction
temperature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves shown in Figure 3.
AMBIENT TEMPERATURE – C
5.0
MAXIMUM POWER DISSIPATION – Watts
4.0
0
–50 80–40 –30 –20 –10 0 10 20 30 40 50 60 70
3.0
2.0
1.0
T
J
= 150C
90
Figure 3. Maximum Power Dissipation vs. Temperature
3&7#
AD8110/AD8111
–6–
Table III. Operation Truth Table
SER/
CE UPDATE CLK DATA IN DATA OUT RESET PAR Operation/Comment
1 X X X X X X No change in logic.
01 f Data
i
Data
i-40
1 0 The data on the serial DATA IN line is loaded
into serial register. The first bit clocked into
the serial register appears at DATA OUT 40
clocks later.
01 f D0 . . . D4, NA in Parallel 1 1 The data on the parallel data lines, D0–D4, are
A0...A2 Mode loaded into the 40-bit serial shift register loca-
tion addressed by A0–A2.
0 0 X X X 1 X Data in the 40-bit shift register transfers into the
parallel latches that control the switch array.
Latches are transparent.
X X X X X 0 X Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
D
CLK
Q
3 TO 8 DECODER
A0
A1
A2
CLK
CE
UPDATE
8
128
DATA IN
(SERIAL)
(OUTPUT
ENABLE)
SER/PAR
RESET
(OUTPUT ENABLE)
OUT0 EN
DATA
OUT
PARALLEL
DATA
D
Q
CLK
D
Q
CLK
D
Q
CLK
D
Q
CLK
D1
D2
D3
D
Q
CLK
D
Q
CLK
D
Q
CLK
D
Q
CLK
D
Q
CLK
OUT1 EN
OUT2 EN
OUT3 EN
OUT4 EN
OUT5 EN
OUT6 EN
OUT7 EN
D
LE
QCLR
OUT7
EN
OUTPUT ENABLE
SWITCH MATRIX
S
D1
Q
D0
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
D
Q
CLK
S
D1
Q
D0
D4
DECODE
D
LE
QCLR
OUT0
EN
D
LE
OUT0
B0
Q
D
LE
Q
OUT0
B1
D
LE
Q
OUT0
B2
D
LE
Q
OUT0
B3
D
LE
OUT1
B0
Q
D
LE
QCLR
OUT6
EN
D
LE
OUT7
B0
Q
D
LE
OUT7
B1
Q
D
LE
OUT7
B2
Q
D
Q
CLK
S
D1
Q
D0
S
D1
Q
D0
D
LE
OUT7
B3
Q
S
D1
Q
D0
Figure 4. Logic Diagram

AD8110ASTZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog & Digital Crosspoint ICs 260 MHz 16 x 8 Buffered
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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