AD7661
Rev. 0 | Page 9 of 28
Pin No. Mnemonic Type
1
Description
16
D7 or
RDC/SDIN
DI/O
When SER/PAR
is LOW, this output is used as Bit 7 of the parallel port data output bus.
When SER/PAR
is HIGH, this input, part of the serial port, is used as either an external data input or a
read mode selection input depending on the state of EXT/INT
.
When EXT/INT
is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results
from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA
with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/INT
is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data
is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT
only when the conversion is complete.
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V).
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground.
21
D8 or
SDOUT
DO
When SER/PAR
is LOW, this output is used as Bit 8 of the parallel port data output bus.
When SER/PAR
is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7661 provides the
conversion result, MSB first, from its internal shift register. The DATA format is determined by the
logic level of OB/2C
. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In
serial mode when EXT/INT is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and
valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and
valid on the next rising edge.
22
D9 or
SCLK
DI/O
When SER/PAR
is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus.
When SER/PAR
is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,
depending upon the logic state of the EXT/INT
pin. The active edge where the data SDOUT is
updated depends upon the logic state of the INVSCLK pin.
23
D10 or
SYNC
DO
When SER/PAR
is LOW, this output is used as Bit 10 of the parallel port data output bus.
When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT
= logic LOW). When a read sequence is
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is
valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW
while the SDOUT output is valid.
24
D11 or
RDERROR
DO
When SER/PAR
is LOW, this output is used as Bit 11 of the parallel port data output bus. When
SER/PAR
and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read error
flag. In slave mode, when a data read is started and not complete when the following conversion is
complete, the current data is lost and RDERROR is pulsed HIGH.
25–28 D[12:15] DO
Bit 12 to Bit 15 of the Parallel Port Data Output
Bus. These pins are always outputs regardless of the
state of SER/PAR
.
29 BUSY DO
Busy Output. Transitions HIGH when a co
nversion is started and remains HIGH until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.
30 DGND P Must Be Tied to Digital Ground.
31
RD
DI
Read Data. When CS
and RD are both LOW, the interface parallel or serial output bus is enabled.
32
CS
DI
Chip Select. When CS
and RD are both LOW, the interface parallel or serial output bus is enabled. CS
is also used to gate the external clock.
33 RESET DI
Reset Input. When set to a logic HIGH, this pin resets the AD7661 and the current conversion, if any,
is aborted. If not used, this pin could be tied to
DGND.
34 PD DI
Power-Down Input. When set to a logic HIGH, power c
onsumption is reduced and conversions are
inhibited after the current one is completed.
35
CNVST
DI
Start Conversion. If CNVST
is HIGH when the acquisition phase (t
8
) is complete, the next falling edge
on CNVST
puts the internal sample/hold into the hold state and initiates a conversion. The mode is
most appropriate if low sampling jitter is desired. If CNVST
is LOW when the acquisition phase (t
8
) is
complete, the internal sample/hold is put into the hold state and a conversion is immediately
started.
37 REF AI/O Reference Input Voltage. On-chip reference output voltage.
38 REFGND AI Reference Input Analog Ground.
39 INGND AI Analog Input Ground.
