AD7661
Rev. 0 | Page 16 of 28
CIRCUIT INFORMATION
SW
A
COMP
SW
B
IN
REF
REFGND
LSB
MSB
32,768C
INGND
16,384C 4C 2C C C
65,536C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
03033-0-020
CNVST
Figure 24. ADC Simplified Schematic
The AD7661 is a very fast, low power, single supply, precise
16-bit analog-to-digital converter (ADC). The AD7661 is
capable of converting 100,000 samples per second (100 kSPS)
and allows power savings between conversions.
The AD7661 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
The AD7661 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in
either a 48-lead LQFP or a 48-lead LFCSP that saves space and
allows flexible configurations as either a serial or parallel inter-
face. The AD7661 is pin-to-pin compatible with PulSAR ADCs
and is an upgrade of the AD7651.
CONVERTER OPERATION
The AD7661 is a successive-approximation ADC based on a
charge redistribution DAC. Figure 24 shows a simplified sche-
matic of the ADC. The capacitive DAC consists of an array of
16 binary weighted capacitors and an additional LSB capacitor.
The comparator’s negative input is connected to a dummy
capacitor of the same value as the capacitive DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator's positive input is connected to AGND
via SW
A
. All independent switches are connected to the analog
input IN. Thus, the capacitor array is used as a sampling
capacitor and acquires the analog signal on IN. Similarly, the
dummy capacitor acquires the analog signal on INGND.
When
CNVST
goes LOW, a conversion phase is initiated. When
the conversion phase begins, SW
A
and SW
B
are opened. The
capacitor array and dummy capacitor are then disconnected
from the inputs and connected to REFGND. Therefore, the
differential voltage between IN and INGND captured at the end
of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between REFGND and REF,
the comparator input varies by binary weighted voltage steps
(V
REF
/2, V
REF
/4, …V
REF
/65536). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition.
After this process is completed, the control logic generates the
ADC output code and brings the BUSY output LOW.
