AD7661
Rev. 0 | Page 22 of 28
DIGITAL INTERFACE
The AD7661 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or a parallel
interface. The serial interface is multiplexed on the parallel data
bus. The AD7661 digital interface also accommodates both 3 V
and 5 V logic by simply connecting the OVDD supply pin of the
AD7661 to the host system interface digital supply. Finally, by
using the OB/
2C
input pin, both twos complement or straight
binary coding can be used.
The two signals,
CS
and
RD
, control the interface.
CS
and
RD
have a similar effect because they are OR’d together internally.
When at least one of these signals is HIGH, the interface
outputs are in high impedance. Usually
CS
allows the selection
of each AD7661 in multicircuit applications and is held low in a
single AD7661 design.
RD
is generally used to enable the
conversion result on the data bus.
PARALLEL INTERFACE
The AD7661 is configured to use the parallel interface when
SER/
PAR
is held LOW. The data can be read either after each
conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 36 and
Figure 37, respectively. When the data is read during the
conversion, however, it is recommended that it is read only
during the first half of the conversion phase. This avoids any
potential feedthrough between voltage transients on the digital
interface and the most critical analog conversion circuitry.
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 38, the LSB byte is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is LOW. When
BYTESWAP is HIGH, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].
SERIAL INTERFACE
The AD7661 is configured to use the serial interface when
SER/
PAR
is held HIGH. The AD7661 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edges of the data clock.
CURRENT
CONVERSION
BUSY
DATA
BUS
t
12
t
13
03033-0-029
RD
CS
Figure 36. Slave Parallel Data Timing for Reading (Read after Convert)
PREVIOUS
CONVERSION
t
1
t
3
t
12
t
13
t
4
BUSY
DATA
BUS
03033-0-030
CNVST,
RD
CS = 0
Figure 37. Slave Parallel Data Timing for Reading (Read during Convert)
CS
RD
BYTESWAP
PINS D[15:8]
PINS D[7:0]
HI-Z
HI-Z
HIGH BYTE LOW BYTE
LOW BYTE HIGH BYTE
HI-Z
HI-Z
t
12
t
12
t
13
03033-0-031
Figure 38. 8-Bit Parallel Interface
