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AD7661ACPZRL

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AD7661
Rev. 0 | Page 3 of 28
SPECIFICATIONS
Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range V
IN
– V
INGND
0 V
REF
V
Operating Input Voltage V
IN
–0.1 +3 V
V
INGND
–0.1 +0.5 V
Analog Input CMRR f
IN
= 10 kHz 68 dB
Input Current 100 kSPS Throughput 1.1 µA
Input Impedance
1
THROUGHPUT SPEED
Complete Cycle 10 µs
Throughput Rate 0 100 kSPS
DC ACCURACY
Integral Linearity Error –2.5 +2.5 LSB
2
No Missing Codes 16 Bits
Differential Linearity Error –1.0 +1.5 LSB
Transition Noise 0.7 LSB
Unipolar Zero Error, T
MIN
to T
MAX
3
±5 LSB
Unipolar Zero Error Temperature Drift
3
±0.25 ppm/°C
Full-Scale Error, T
MIN
to T
MAX
3
REF = 2.5 V ±0.08 % of FSR
Full-Scale Error Temperature Drift ±0.4 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% ±2 LSB
AC ACCURACY
Signal-to-Noise f
IN
= 20 kHz 88 89.3 dB
4
Spurious Free Dynamic Range f
IN
= 20 kHz 96 107 dB
Total Harmonic Distortion f
IN
= 20 kHz –107 –96 dB
Signal-to-(Noise + Distortion) f
IN
= 20 kHz 88 89.3 dB
–60 dB Input, f
IN
= 20 kHz 30 dB
–3 dB Input Bandwidth 820 kHz
SAMPLING DYNAMICS
Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 8.75 µs
REFERENCE
Internal Reference Voltage V
REF
@ 25°C 2.48 2.5 2.52 V
Internal Reference Temperature Drift –40°C to +85°C ±3 ±15 ppm/°C
Output Voltage Hysteresis –40°C to +85°C 50 ppm
Long Term Drift 100 ppm/1000 Hours
Line Regulation AVDD = 5 V ± 5% ±15 ppm/V
Turn-On Settling Time C
REF
= 10 µF 5 ms
Temperature Pin
Voltage Output @ 25°C 300 mV
Temperature Sensitivity 1 mV/°C
Output Resistance 4.3 kΩ
External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V
External Reference Current Drain 100 kSPS Throughput 35 µA
AD7661
Rev. 0 | Page 4 of 28
Parameter Conditions Min Typ Max Unit
DIGITAL INPUTS
Logic Levels
V
IL
–0.3 +0.8 V
V
IH
2.0 DVDD + 0.3 V
I
IL
–1 +1 µA
I
IH
–1 +1 µA
DIGITAL OUTPUTS
Data Format
5
Pipeline Delay
6
V
OL
I
SINK
= 1.6 mA 0.4 V
V
OH
I
SOURCE
= –500 µA OVDD – 0.6 V
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.25
7
V
Operating Current 100 kSPS Throughput
AVDD
8
With Reference and Buffer 6.2 mA
AVDD
9
Reference and Buffer Alone 3 mA
DVDD
10
1.75 mA
OVDD
10
21 µA
Power Dissipation without REF
10
100 kSPS Throughput 16 25 mW
1 kSPS Throughput 160 µW
Power Dissipation with REF
10
100 kSPS Throughput 40 45 mW
TEMPERATURE RANGE
11
Specified Performance T
MIN
to T
MAX
–40 +85 °C
1
See Analog Input section.
2
LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV.
3
See Definitions of Specifications section. These specifications do not include the error contribution from the external reference.
4
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5
Parallel or Serial 16-Bit.
6
Conversion results are available immediately after completed conversion.
7
The max should be the minimum of 5.25 V and DVDD + 0.3 V.
8
With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH.
9
With PDREF, PDBUF LOW and PD HIGH.
10
Tested in parallel reading mode
11
Consult factory for extended temperature range.
AD7661
Rev. 0 | Page 5 of 28
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
Parameter Symbol Min Typ Max Unit
Refer to Figure 33 and Figure 34
Convert Pulse Width t
1
10 ns
Time between Conversions t
2
10 µs
CNVST LOW to BUSY HIGH Delay
t
3
35 ns
BUSY HIGH All Modes Except Master Serial Read after Convert t
4
1.25 µs
Aperture Delay t
5
2 ns
End of Conversion to BUSY LOW Delay t
6
10 ns
Conversion Time t
7
1.25 µs
Acquisition Time t
8
8.75 µs
RESET Pulse Width t
9
10 ns
Refer to Figure 35, Figure 36, and Figure 37 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t
10
1.25 µs
DATA Valid to BUSY LOW Delay t
11
12 ns
Bus Access Request to DATA Valid t
12
45 ns
Bus Relinquish Time t
13
5 15 ns
Refer to Figure 39 and Figure 40 (Master Serial Interface Modes)
1
CS LOW to SYNC Valid Delay
t
14
10 ns
CS LOW to Internal SCLK Valid Delay
1
t
15
10 ns
CS LOW to SDOUT Delay
t
16
10 ns
CNVST LOW to SYNC Delay
t
17
525 ns
SYNC Asserted to SCLK First Edge Delay t
18
3 ns
Internal SCLK Period
2
t
19
25 40 ns
Internal SCLK HIGH
2
t
20
12 ns
Internal SCLK LOW
2
t
21
7 ns
SDOUT Valid Setup Time
2
t
22
4 ns
SDOUT Valid Hold Time
2
t
23
2 ns
SCLK Last Edge to SYNC Delay
2
t
24
3 ns
CS HIGH to SYNC HI-Z
t
25
10 ns
CS HIGH to Internal SCLK HI-Z
t
26
10 ns
CS HIGH to SDOUT HI-Z
t
27
10 ns
BUSY HIGH in Master Serial Read after Convert
2
t
28
See Table 4
CNVST LOW to SYNC Asserted Delay
t
29
1.25 µs
SYNC Deasserted to BUSY LOW Delay t
30
25 ns
Refer to Figure 41 and Figure 42 (Slave Serial Interface Modes)
1
External SCLK Setup Time t
31
5 ns
External SCLK Active Edge to SDOUT Delay t
32
3 18 ns
SDIN Setup Time t
33
5 ns
SDIN Hold Time t
34
5 ns
External SCLK Period t
35
25 ns
External SCLK HIGH t
36
10 ns
External SCLK LOW t
37
10 ns
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
2
In serial master read during convert mode. See Table 4 for serial master read after convert mode.
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AD7661ACPZRL

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Buy AD7661ACPZRL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit 100kSPS Unipolar w/ Ref
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New from this manufacturer.
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