The normal watchdog timeout period (t
WD
) is active
after the initial watchdog timer and continues to be
active until the watchdog timer expires. The normal
watchdog timeout period monitors a pulsed output of
the µP that indicates when normal processor behavior
occurs. If no pulse occurs during the normal watchdog
timeout period, this indicates that the processor has
stopped operating or is stuck in an infinite execution
loop and WDO asserts. Disable or enable the watch-
dog timer through R15h[7].
If RESET is programmed to depend on WDO and the
watchdog timer expires, WDO will assert for a short
pulse, just long enough to assert RESET (typically less
than 5µs; see Figure 4). If WDO is not programmed to
depend on RESET and the watchdog timer expires,
WDO will remain asserted until a low-to-high or high-to-
low edge occurs on WDI. Program WDO for open-drain
or weak pullup (see Table 8).
Fault Register
Registers 28h to 2Ah store all fault conditions including
undervoltage, overvoltage, and watchdog timer faults
(see Table 9). Fault registers are read-only and lose
contents upon power removal. The first read command
from the fault registers after power-up gives invalid
data. Reading the fault register clears all fault flags in
the register.
MAX6884/MAX6885
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
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