MAX6884/MAX6885
Note that once the read has been done, the internal point-
er is increased by one, unless a memory boundary is hit.
If the device is busy or if the address is not an allowed
one, the command code is NACKed and the internal
address pointer is not altered. The master must then inter-
rupt the communication issuing a STOP condition.
Block Read
The block read protocol allows the master device to
read a block of 16 bytes from the EEPROM or register
bank (see Figure 11). Read fewer than 16 bytes of data
by issuing an early STOP condition from the master, or
by generating a NACK with the master. Previous actions
through the serial interface predetermine the first source
address. It is suggested to use a send byte protocol,
before the block read, to set the initial read address.
The block read protocol is initiated with a command
code of C1h. The block read procedure follows:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends 8 bits of the block read com-
mand (C1h).
5) The slave asserts an ACK on SDA, unless busy.
6) The master generates a repeated START condition.
7) The master sends the 7-bit slave address and a
read bit (high).
8) The slave asserts an ACK on SDA.
9) The slave sends the 8-bit byte count (16).
10) The master asserts an ACK on SDA.
11) The slave sends 8 bits of data.
12) The master asserts an ACK on SDA.
13) Repeat steps 8 and 9 15 times.
14) The master generates a STOP condition.
Address Pointers
Use the send byte protocol to set the register address
pointers before read and write operations. For the con-
figuration registers, valid address pointers range from
00h to 2Fh. Register addresses outside of this range
result in a NACK being issued from the MAX6884/
MAX6885. When using the block write protocol, the
address pointer automatically increments after each
data byte, except when the address pointer is already
at 2Fh. If the address pointer is already 2Fh, and more
data bytes are being sent, these subsequent bytes
overwrite address 2Fh repeatedly, but no data will be
left in 2Fh as this is a read-only address.
For the configuration EEPROM, valid address pointers
range from 80h to 9Fh. When using the block write pro-
tocol, the address pointer automatically increments
after each data byte, except when the address pointer
is already at 9Fh. If the address pointer is already 9Fh,
and more data bytes are being sent, these subsequent
bytes overwrite address 9Fh repeatedly, leaving only
the last data byte sent stored at this register address.
For the user EEPROM, valid address pointers range from
40h to 7Fh. As for the configuration EEPROM, block write
and block read protocols can also be used. The internal
address pointer will automatically increment up to the
user EEPROM boundary 7Fh where the pointer moves to
the first address of the configuration memory section
80h, as there is no forbidden address in the middle.
Applications Information
Configuration Download at Power-Up
The configuration of the MAX6884/MAX6885 (undervolt-
age/overvoltage thresholds, reset time delays, watch-
dog behavior, programmable output conditions and
configurations, etc.) at power-up depends on the con-
tents of the EEPROM. The EEPROM is comprised of
buffered latches that store the configuration. The local
volatile memory latches lose their contents at power-
down. Therefore, at power-up, the device configuration
must be restored by downloading the contents of the
EEPROM (nonvolatile memory) to the local latches. This
download occurs in a number of steps:
1) Programmable outputs are high impedance with no
power applied to the device.
2) When V
CC
or IN1–IN4 (see the Powering the
MAX6884/MAX6885 section) exceeds +1V, all pro-
grammable outputs are asserted low.
3) When V
CC
or IN1–IN4 exceeds UVLO (2.5V), the
configuration EEPROM starts to download its con-
tents to the volatile configuration registers. The
download takes 2.5ms (max). The programmable
outputs assume their programmed conditional out-
put state when V
CC
or IN1–IN4 exceeds the UVLO
(see the Powering the MAX6884/MAX6885 section).
4) Any attempt to communicate with the device prior
to this download completion results in a NACK
being issued from the MAX6884/MAX6885.
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
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