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STM8AL3LE88TCX

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
Silicon limitations STM8AL3xxx STM8L052R8 STM8L1xxx6/8
10/18 DocID17922 Rev 6
1.1.6 Incorrect code execution when FLASH/EEPROM memory wakes up
from power down mode
Description
In case FLASH/EEPROM memory is put in power down mode (I
DDQ
), first read after
wakeup could return an incorrect content when F
CPU
is above 8 MHz + 5%.
FLASH/EEPROM memory is put in I
DDQ
mode by default during Halt mode and could be
forced to I
DDQ
mode by software for wait mode and during RAM execution.
As a consequence, following behavior may be seen on some devices:
After wakeup from Low power mode with FLASH memory in I
DDQ
mode, program
execution gets lost due to incorrect read of vector table.
Code running from RAM read an incorrect value from FLASH/EEPROM memory, when
forced in I
DDQ
mode.
Program execution gets corrupted when returning from RAM execution to FLASH
memory execution in case FLASH memory is forced in I
DDQ
mode.
Workaround
Slow down F
SYSCLK
before entering Low power mode to ensure correct FLASH memory
wakeup. This could be done using clock divider (CLK_CKDIVR) or by activation of fast
wakeup feature by setting FHWU bit in CLK_ICKCR register. Original clock setting can be
reconfigured back by software after wakeup.
Code example, assuming no divider is used in application by default.
CLK_CKDIVR = 0x01;
_asm(“HALT”);
CLK_CKDIVR = 0x00;
The interrupt service routine executed after wakeup could either stay at slower clock speed,
or reconfigure clock setting. Care has to be taken to restore previous clock divider at the end
of interrupt routines when modifying clock divider.
No fix planned for this limitation.
DocID17922 Rev 6 11/18
STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Silicon limitations
17
1.2 System limitations
1.2.1 Default DAC output level when output buffer is enabled
Description
When the DAC is enabled in buffered mode configuration, the output is set to a voltage
which corresponds to the code 0xFFF, whatever the data output register value. The output
recovers the correct voltage as soon as a new data is written into the data holding register.
Workaround
None.
The following software sequence must be executed at the highest speed to limit the duration
of this transient behavior:
DAC->CR1=01; //Enable DAC
DAC->DHR8 = 0x0; //Update the data holding register with 0 (as
an example), or with any other data.
Note: The DAC in unbuffered mode is not affected by this limitation.
1.2.2 32.768 kHz LSE crystal accuracy may be disturbed by the use of
adjacent I/Os
Description
The activity on the PC4 and PC7 I/Os (input or output) can lead to missing pulses on the low
speed external oscillator (32.768 kHz external crystal).
Workaround
None.
If a high LSE accuracy is required, PC4 and PC7 must be tied to V
DD
or V
SS
.
No fix planned for this limitation.
1.2.3 RTC LSE failure can be detected just once after power-on reset
Description
When the CSS on LSE is enabled (CSSEN=1 in CSSLSE_CSR), the CSS on LSE Flag
(CSSF) can be set only once after power-on reset. Consequently, in case of several LSE
perturbations in the application, only the first one can be detected and set the CSSF flag.
Workaround
None.
No fix planned for this limitation.
Silicon limitations STM8AL3xxx STM8L052R8 STM8L1xxx6/8
12/18 DocID17922 Rev 6
1.3 Peripheral limitations
1.3.1 SPI2 peripheral limitations
SPI2_MOSI cannot be configured as pseudo open-drain on 48-pin packages
Description
On UFQFPN48 and LQFP48 packages, when the SPI2 peripheral is enabled and
SPI2_MOSI/PD5 is configured as pseudo open-drain output in the GPIO Port D control
register 1 (PD_CR1), PD5 remains in push-pull mode.
SPI2_MOSI can be configured as pseudo open-drain output on LQFP80 and LQFP64
packages.
Workaround
None. However, as SPI2_MOSI is usually configured as push-pull output, this limitation
should not have any impact.
No fix planned for this limitation.
1.3.2 I2C peripheral limitations
I2C event management
Description
As described in the I2C section of the STM8L05x/15x microcontroller family reference
manual (RM0031), the application firmware has to manage several software events before
the current byte is transferred. If the EV7, EV7_1, EV6_1, EV6_3, EV2, EV8 and EV3
events are not managed before the current byte is transferred, problems may occur such as
receiving an extra byte, reading the same data twice or missing data.
Workarounds
When the EV7, EV7_1, EV6_1, EV6_3, EV2, EV8, and EV3 events cannot be managed
before the current byte transfer and before the acknowledge pulse when the ACK control bit
changes, it is recommended to:
1. Use the I
2
C with DMA in general, except when the Master is receiving a single byte.
2. Use I
2
C interrupts in nested mode and boost their priorities to the highest one in the
application to make them uninterruptible.
No fix planned for this limitation.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

STM8AL3LE88TCX

Mfr. #:
Buy STM8AL3LE88TCX
Manufacturer:
STMicroelectronics
Description:
8-bit Microcontrollers - MCU 8 BITS MICROCONTR
Lifecycle:
New from this manufacturer.
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