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STM8AL3LE88TCX

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
DocID17922 Rev 6 7/18
STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Silicon limitations
17
Workaround 2
To optimize the number of cycles added by workaround 1, you can use this workaround
instead. Workaround 2 can be used in applications with fixed interrupt priorities, identified at
the program compilation phase:
push #value
pop cc
where bits 5 and 3 of #value have to be configured according to interrupt priority given by I1
and I0, and bit 6 kept cleared.
In this case, compiler workaround 1 has to be disabled by using compiler directives.
No fix is planned for this limitation.
1.1.4 Incorrect code execution when WFE execution is interrupted by ISR
or event
Description
Two types of failures can occur:
Case 1:
In case WFE instruction is placed in the two MSB of the 32-bit word within the memory,
an event which occurs during the WFE execution cycle or re-execution cycle (when
returning from ISR handler) will cause an incorrect code execution.
Case 2:
An interrupt request, which occurs during the WFE execution cycle will lead to incorrect
code execution. This is also valid for the WFE re-execution cycle, while returning from
an ISR handler.
The above failures have no impact on the core behavior when the ISR request or events
occur in Wait for Event mode itself, out of the critical single cycle of WFE instruction
execution.
Workaround
General solution is to ensure no interrupt request or event occurs during WFE instruction
execution or re-execution cycle by proper application timing.
Dedicated workarounds:
Case 1:
Replace the WFE instruction with
WFE
JRA next
next:
Silicon limitations STM8AL3xxx STM8L052R8 STM8L1xxx6/8
8/18 DocID17922 Rev 6
Case 2:
It is recommended to avoid any interrupts before WFE mode is entered. This can be
done by disabling all interrupts before the device enters Wait for event mode.
SIM
WFE
RIM
This workaround also prevents WFE re-execution in case 1.
No fix is planned for this limitation.
1.1.5 Core kept in stall mode when DMA transfer occurs during program/
erase operation to EEPROM
Description
When the MCU performs EEPROM program/erase operation, the core is stalled during data
transfer to the memory controller, which occurs at the beginning of the program/erase
operation. If a DMA request servicing starts while the core is stalled, the core does not
return from stall mode to program execution.
The core is stalled for 11 cycles during byte program/erase, 8 cycles during word
program/erase and 3 cycles during each word transfer in block programming mode. For
block erase, the core is stalled for 127 cycles.
When a DMA request arises, it is only served if the DMA priority is higher than the core
access priority.
If the current DMA priority is lower than the core one, the DMA service is delayed until the
core access becomes idle.
The DMA also includes a programmable timeout function, configurable by DMA_GCSR
register. If the core does not release the bus during this timeout, the DMA automatically
increases its own priority and forces the core to release the bus for DMA service.
No fix is planned for this limitation.
Several workarounds are available for this limitation.
Workaround 1
Disable all DMA requests during data transfer to the EEPROM.
This workaround is applicable for all program/erase operations.
Workaround 2
Configure DMA programmable timeout in the DMA_GCSR register to exceed the number of
stall cycles required during the transfer. DMA priority must never be configured to a very
high level.
This workaround is applicable for all program/erase operations except block erase.
In order to apply this workaround to block erase, use block programming to 0x00 instead of
block erase. This takes ~6
ms instead of ~3 ms.
DocID17922 Rev 6 9/18
STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Silicon limitations
17
Workaround 3
This workaround can be used if block erase cannot be replaced by block programming.
In this workaround, DMA is used to transfer data to the EEPROM instead of the core. All
other DMA transfers are delayed once the core is stalled due to data transfer to memory
controller.
/* start of the workaround in user code, using FW Library */
#ifdef USE_EVENT_MODE
DMA1_Channel3->CCR= DMA_CCR_MEM | DMA_CCR_IDM | DMA_CCR_TCIE; /*
Config DMA Chn3 Mem, incr, disable, interrupt) */
#else
DMA1_Channel3->CCR= DMA_CCR_MEM | DMA_CCR_IDM; /* Config DMA
Chn3 (Mem, incr,disable) */
#endif
DMA1_Channel3->CM0ARH= (uint8_t)0; /* Source address */
DMA1_Channel3->CM0ARL= (uint8_t)0;
DMA1_Channel3->CPARH= (uint8_t)(addr_begin >> 8); /* Destination
address */
DMA1_Channel3->CPARL= (uint8_t)(addr_begin);
DMA1_Channel3->CNBTR= 2; /* Number of data to be transferred */
DMA1_Channel3->CSPR= 8; /* Low priority, 16 bit mode */
DMA1_Channel3->CSPR &= ~DMA_CSPR_TCIF;/* Clear TCIF */
DMA1->GCSR|= 1; /* Global DMA enable */
#ifdef USE_EVENT_MODE
WFE->CR3 = WFE_CR3_DMA1CH23_EV; /* Enable event generation on
DMA */
#endif
FLASH->DUKR = 0xAE; /* Unprotect data memory */
FLASH->DUKR = 0x56;
while((FLASH->IAPSR & FLASH_IAPSR_DUL) == 0)
{} /* Polling DUL */
FLASH_Block_Load();
/* end of the workaround in user code */
/* following routine has to be placed in the RAM */
void FLASH_Block_Load(){
__asm("sim\n"); /* Disable interrupts */
FLASH->CR2 |= FLASH_CR2_ERASE; /* Enable erase block mode */
DMA1_Channel3->CCR|= DMA_CCR_CE; /* Enable DMA MEM transfer */
#ifdef USE_EVENT_MODE
__asm("wfe"); /* Wait for end of DMA operation */
#else
while((DMA1_Channel3->CSPR & DMA_CSPR_TCIF) == 0)
{} /* Polling for end of DMA operation */
#endif
__asm("rim\n"); /* Enable interrupts */
}
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STM8AL3LE88TCX

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Manufacturer:
STMicroelectronics
Description:
8-bit Microcontrollers - MCU 8 BITS MICROCONTR
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