Silicon limitations STM8AL3xxx STM8L052R8 STM8L1xxx6/8
6/18 DocID17922 Rev 6
1.1 Core limitations
1.1.1 Interrupt service routine (ISR) executed with priority of main process
Description
If an interrupt is cleared or masked when the context saving has already started, the
corresponding ISR is executed with the priority of the main process.
Workaround
None.
No fix is planned for this limitation.
1.1.2 Main CPU execution is not resumed after an ISR resets the AL bit
Description
If the CPU is in wait for interrupt state and the AL bit is set, the CPU returns to wait for
interrupt state after executing an ISR. To continue executing the main program, the AL bit
must be reset by the ISR. When AL is reset just before exiting the ISR, the CPU may remain
stalled.
Workaround
Reset the AL bit at least two instructions before the IRET instruction.
No fix is planned for this limitation.
1.1.3 Unexpected DIV/DIVW instruction result in ISR
Description
In very specific conditions, a DIV/DIVW instruction may return a false result when executed
inside an interrupt service routine (ISR). This error occurs when the DIV/DIVW instruction is
interrupted and a second interrupt is generated during the execution of the IRET instruction
of the first ISR. Under these conditions, the DIV/DIVW instruction executed inside the
second ISR, including function calls, may return an unexpected result.
The applications that do not use the DIV/DIVW instruction within ISRs are not impacted.
Workaround 1
If an ISR or a function called by this routine contains a division operation, the following
assembly code should be added inside the ISR before the DIV/DIVW instruction:
push cc
pop a
and a,#$BF
push a
pop cc
This sequence should be placed by C compilers at the beginning of the ISR using
DIV/DIVW. Refer to your compiler documentation for details on the implementation and
control of automatic or manual code insertion.
