Silicon limitations STM8AL3xxx STM8L052R8 STM8L1xxx6/8
14/18 DocID17922 Rev 6
Workaround
In the I²C standard, it is allowed to send a Stop only at the end of the full byte (8 bits +
acknowledge), so this scenario is not allowed. Other derived protocols like CBUS allow it,
but they are not supported by the I²C peripheral.
In case of noisy environment in which unwanted bus errors can occur, it is recommended to
implement a timeout to ensure that the SB (start bit) flag is set after the START control bit is
set. In case the timeout has elapsed, the peripheral must be reset by setting the SWRST bit
in the I2C_CR2 control register. The I
2
C peripheral should be reset in the same way if a
BERR is detected while the START bit is set in I2C_CR2.
No fix is planned for this limitation.
Violation of I
2
C “setup time for repeated START condition” parameter
Description
In case of a repeated Start, the “setup time for repeated START condition” parameter
(named t
SU(STA)
in the datasheet and Tsu:sta in the I
2
C specifications) may be slightly
violated when the I
2
C operates in Master Standard mode at a frequency ranging from 88 to
100
kHz. t
SU(STA)
minimum value may be 4 µs instead of 4.7 µs.
The issue occurs under the following conditions:
1. The I
2
C peripheral operates in Master Standard mode at a frequency ranging from 88
to 100
kHz (no issue in Fast mode)
2. and the SCL rise time meets one of the following conditions:
– The slave does not stretch the clock and the SCL rise time is more than 300 ns
(the issue cannot occur when the SCL rise time is less than 300 ns).
– or the slave stretches the clock.
Workaround
Reduce the frequency down to 88 kHz or use the I
2
C Fast mode if it is supported by the
slave.
In I
2
C slave “NOSTRETCH” mode, underrun errors may not be detected
and may generate bus errors
Description
The data valid time (t
VD;DAT
, t
VD;ACK
) described by the I
2
C specifications may be violated as
well as the maximum current data hold time (t
HD;DAT
) under the conditions described below.
In addition, if the data register is written too late and close to the SCL rising edge, an error
may be generated on the bus: SDA toggles while SCL is high. These violations cannot be
detected because the OVR flag is not set (no transmit buffer underrun is detected).
This issue occurs under the following conditions:
1. The I
2
C peripheral operates In Slave transmit mode with clock stretching disabled
(NOSTRETCH=1)
2. and the application is late to write the DR data register, but not late enough to set the
OVR flag (the data register is written before the SCL rising edge).
