OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD1974WBSTZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet AD1974
Rev. D | Page 15 of 24
ALRCLK
ABCLK
FOUR ADC CHANNELS OF
THE SECOND IC IN THE CHAIN
FOUR ADC CHANNELS OF
THE FIRST IC IN THE CHAIN
ADCL1 ADCR1 ADCL2 ADCR2 ADCL1 ADCR1 ADCL2 ADCR2 UNUSED
UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
ASDATA1 (TDM_OUT
OF THE SECOND AD1974
IN THE CHAIN)
ADCL1 ADCR1 ADCL2 ADCR2
ASDATA2 (TDM_IN
OF THE SECOND AD1974
IN THE CHAIN)
32 BITS
MSB
DSP
SECOND
AD1974
FIRST
AD1974
06614-057
Figure 10. ADC TDM Daisy-Chain Mode (512 f
S
ABCLK, Two AD1974 Daisy Chains)
ALRCLK
ABCLK
ASDATA
ALRCLK
ABCLK
ASDATA
ALRCLK
ABCLK
ASDATA
LSB LSB
LSB
LSB
LSB LSB
LEFT CHANNEL RIGHT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
LEFT CHANNEL RIGHT CHANNEL
MSB MSB
MSB
MSB
MSB MSB
RIGHT JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
I
2
S MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
ALRCLK
ABCLK
ASDATA
LSB LSB
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT
f
S
EXCEPT FOR DSP MODE WHICH IS 2 × f
S.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
MSB MSB
1/
f
S
06614-013
Figure 11. Stereo Serial Modes
AD1974 Data Sheet
Rev. D | Page 16 of 24
06614-014
AUXBCLK
AUXRCLK
AUXDATA
LEFT JUSTIFIED
MODE
AUXDATA
RIGHT JUSTIFIED
MODE
AUXDATA
I
2
S JUSTIFIED
MODE
t
XDH
t
XDH
t
XDH
t
XDS
t
XDS
t
XDH
t
XDS
t
XLH
t
XDS
t
XLS
t
XBL
t
XBH
MSB
LSB
MSB
MSB–1MSB
Figure 12. Auxiliary Serial Timing
ABCLK
ALRCLK
ASDATA
LEFT JUSTIFIED
MODE
ASDATA
RIGHT JUSTIFIED
MODE
ASDATA
I
2
S JUSTIFIED
MODE
t
ABH
LSB
MSB
MSB
MSB
MSB–1
t
ABL
t
ALS
t
ABDD
t
ABDD
t
ABDD
t
ALH
0
6614-015
Figure 13. ADC Serial Timing
Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12)
Pin Name Stereo Mode TDM Mode AUX Mode
ASDATA1 ADC1 data output ADC TDM data output ADCTDM data output
ASDATA2 ADC2 data output ADC TDM data input Not used (float)
AUXDATA1 Not used (ground) Not used (ground) AUXDATA in 1 (from external ADC1)
AUXDATA2 Not used (ground) Not used (ground) AUXDATA in 2 (from external ADC2)
ALRCLK ADC LRCLK input/output ADC TDM Frame Sync input/output ADCTDM frame sync input/output
ABCLK ADC BCLK input/output ADC TDM BCLK input/output ADCTDM BCLK input/output
AUXLRCLK Not used (ground) Not used (ground) AUXLRCLK input/output
AUXBCLK Not used (ground) Not used (ground) AUXBCLK input/output
Data Sheet AD1974
Rev. D | Page 17 of 24
AUX
ADC 1
LRCLK
BCLK
DATA
MCLK
AUX
ADC 2
LRCLK
BCLK
DATA
MCLK
30MHz
12.288MHz
SHARC IS RUNNING
IN SLAVE MODE
(INTERRUPT-DRIVEN)
SHARC
AD1974
TDM MASTER
AUX MASTER
FSYNC-TDM (RFS)
RxCLK
RxDATA
TxCLK
TFS (NC)
AUXBCLK
AUXLRCLK
AUXDATA1
AUXDATA2
MCLK
ASDATA1
ALRCLK ABCLK
06614-019
Figure 14. Example of AUX Mode Connection to SHARC® (AD1974 as TDM Master/AUX Master Shown)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD1974WBSTZ-RL

Mfr. #:
Buy AD1974WBSTZ-RL
Manufacturer:
Analog Devices Inc.
Description:
Audio A/D Converter ICs 4 Channel ADC with On-Chip PLL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet