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AD1974WBSTZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
AD1974 Data Sheet
Rev. D | Page 18 of 24
CONTROL REGISTERS
The global address for the AD1974 is 0x04, shifted left one bit due to the R/
W
bit. All registers are reset to 0.
Note that the first setting in each control register parameter is the default setting.
Table 14. Register Format
Global Address R/
W
Register Address Data
Bit
23:17 16 15:8 7:0
Table 15. Register Addresses Description
Address Function
0 PLL and Clock Control 0
1 PLL and Clock Control 1
2 AUXPORT Control 0
3 AUXPORT Control 1
4 AUXPORT Control 2
5 Reserved
6 Reserved
7 Reserved
8 Reserved
9 Reserved
10 Reserved
11 Reserved
12 Reserved
13 Reserved
14 ADC Control 0
15
ADC Control 1
16 ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0
Bit Value Function Description
0 0 Normal operation PLL power-down
1 Power-down
2:1 00 INPUT 256 (×44.1 kHz or 48 kHz) MCLKI/XI pin functionality (PLL active), master clock rate setting
01
INPUT 384 (×44.1 kHz or 48 kHz)
10 INPUT 512 (×44.1 kHz or 48 kHz)
11 INPUT 768 (×44.1 kHz or 48 kHz)
4:3 00 XTAL oscillator enabled MCLKO/XO pin, master clock rate setting
01 256 × f
S
VCO output
10 512 × f
S
VCO output
11 Off
6:5 00 MCLKI/XI PLL input
01 AUXLRCLK
10 ALRCLK
11 Reserved
7 0 Disable: ADC idle Internal MCLK enable
1 Enable: ADC active
Data Sheet AD1974
Rev. D | Page 19 of 24
Table 17. PLL and Clock Control 1
Bit Value Function Description
0 0 PLL clock AUXPORT clock source select
1 MCLK
1 0 PLL clock ADC clock source select
1 MCLK
2 0 Enabled On-chip voltage reference
1 Disabled
3 0 Not locked PLL lock indicator (read only)
1 Locked
7:4 0000 Reserved
AUXPORT CONTROL REGISTERS
Table 18. AUXPORT Control 0
Bit Value Function Description
0 0 Reserved Reserved
1 Reserved
2:1 00 32 kHz/44.1 kHz/48 kHz Sample rate
01 64 kHz/88.2 kHz/96 kHz
10 128 kHz/176.4 kHz/192 kHz
11 Reserved
5:3 000 1 AUXDATA delay (AUXBCLK periods)
001 0
010 8
011
12
100 16
101 Reserved
110 Reserved
111 Reserved
7:6 00 Stereo (normal) Serial format
01 Reserved
10 ADC AUX mode (ADC-, TDM-coupled)
11 Reserved
Table 19. AUXPORT Control 1
Bit Value Function Description
0 0 Reserved
1 Reserved
2:1 00 64 (two channels) AUXBCLKs per frame
01 Reserved
10 Reserved
11 Reserved
3 0 Left low AUXLRCLK polarity
1 Left high
4 0 Slave AUXLRCLK master/slave
1 Master
5 0 Slave AUXBCLK master/slave
1 Master
6 0 AUXBCLK pin AUXBCLK source
1 Internally generated
7 0 Normal AUXBCLK polarity
1 Inverted
AD1974 Data Sheet
Rev. D | Page 20 of 24
Table 20. AUXPORT Control 2
Bit Value Function Description
0
0
Reserved
1 Reserved
2:1 00 Reserved
01 Reserved
10 Reserved
11 Reserved
4:3 00 24 Word width
01 20
10 Reserved
11 16
5 0 Reserved
1 Reserved
7:6 00 Reserved
ADC CONTROL REGISTERS
Table 21. ADC Control 0
Bit Value Function Description
0 0 Normal Power-down
1 Power down
1 0 Off High-pass filter
1 On
2 0 Unmute ADC1L mute
1 Mute
3 0 Unmute ADC1R mute
1 Mute
4 0 Unmute ADC2L mute
1 Mute
5 0 Unmute ADC2R mute
1 Mute
7:6 00 32 kHz/44.1 kHz/48 kHz Output sample rate
01
64 kHz/88.2 kHz/96 kHz
10 128 kHz/176.4 kHz/192 kHz
11 Reserved
Table 22. ADC Control 1
Bit Value Function Description
1:0 00 24 Word width
01 20
10 Reserved
11 16
4:2 000 1 SDATA delay (BCLK periods)
001 0
010 8
011 12
100 16
101 Reserved
110 Reserved
111 Reserved
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD1974WBSTZ-RL

Mfr. #:
Buy AD1974WBSTZ-RL
Manufacturer:
Analog Devices Inc.
Description:
Audio A/D Converter ICs 4 Channel ADC with On-Chip PLL
Lifecycle:
New from this manufacturer.
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