OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

S1V30120F01A100

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
6. Electrical Characteristics
10 EPSON S1V30120 Hardware Specification (Rev. 1.2)
Parameter Symbol Condition Min. Typ. Max. Unit
Output characteristic Pin names: SIN, SCLK, GPIOA[11:0], AUDCLK, HPOP, SPPDN, SPHMT
TDO, HPON
H-level output voltage VOH1 HVDD=3.0V
IOH=-2mA
HVDD-0.4 - - V
L-level output voltage VOL1 HVDD=3.0V
IOL=2mA
- - VSS+0.4 V
Output characteristic Pin name: SOUT,SFRM1,SFRM2
H-level output voltage VOH2 HVDD=3.0V
IOH=-8mA
HVDD-0.4 - - V
L-level output voltage VOL2 HVDD=3.0V
IOL=8mA
- - VSS+0.4 V
Output characteristic Pin names: SIN, SCLK, SFRM1, SFRM2, SPPDN, SPHMT, AUDCLK,
HPOP, HPON, SOUT, GPIOA[11:0], TDO
Off-state leakage
current
IOZ HVDD=3.6V
HVOH=HVDD
VOL=VSS
-5 - 5 A
Parameter Symbol Condition Min. Typ. Max. Unit
Output characteristic Pin names: All input pins
Input pin
capacitance
CI f=1MHz
HVDD=LVDD=AVDD=
PLLVDD=0V
- - 8 pF
Pin capacitance Pin names: All output pins except HPO
Output pin
capacitance
CO1 f=1MHz
HVDD=LVDD=AVDD=
PLLVDD=0V
- - 8 pF
Pin capacitance Pin names: All output pins
I/O pin
capacitance
CIO f=1MHz
HVDD=LVDD=AVDD=
PLLVDD=0V
- - 8 pF
6. Electrical Characteristics
S1V30120 Hardware Specification (Rev. 1.2) EPSON 11
6.4 AC Characteristics
6.4.1 Clock Timing
90% HV
IH
10% HV
IL
t
PWH
t
PWL
t
r
t
f
T
OSC
t
CJper
t
cycle1
t
cycle2
Fig. 6-1 Clock Timing
Symbol Parameter Min. Typ. Max. Unit
f
OSC
Input clock frequency - 32.768 - kHz
T
OSC
Input clock period - 1/fosc - s
t
pwh
Input clock pulse width high 5 - - s
t
pw
ｌ
Input clock pulse width low 5 - - s
t
r
Input clock rising time (10% ->90%) - - 12 s
t
f
Input clock falling time (90%->10%) - - 12 s
t
CJper
Input clock period jitter (*2, 4) -10 - 10 ns
t
CJcycle
Input clock cycle jitter (*1, 3, 4) -10 - 10 ns
*1 t
CJcycle
= t
cycle1
- t
cycle2
*2 The input clock period jitter is the displacement relative to the center period (reciprocal of center
frequency).
*3 The input clock cycle jitter is difference in period between adjacent cycles.
*4 The jitter characteristics must meet both t
Cjper
and t
Cjcycle
characteristics.
6. Electrical Characteristics
12 EPSON S1V30120 Hardware Specification (Rev. 1.2)
6.4.2 Initialization Timing
6.4.2.1 Power-on/Reset Timing
LVDD
PLLVDD
(AVDD)
HVDD
(AVDD)
NRESET
CLKI
t
1
t
3
t
2
t
4
t
4
Fig. 6-2 Power-on/Reset Timing
Symbol Parameter Min. Max. Unit
t
1
Delay from the LVDD and PLLVDD (AVDD) power-on to HVDD
(AVDD) power-on
*
1
10 - s
t
2
Minimum delay from the HVDD power-on to theCLK1 rising edge
before NRESET release
100 - s
t
3
The minimum RESET assertion on system power up 2 - T
OSC
*
2
t
4
NRESET synchronization time
(Number of clock cycles before NRESET is applied internally)
2 - T
OSC
*
2
*1 See Section 6.2 Recommended Operating Conditions.
*2 T
OSC
is the CLKI clock period.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

S1V30120F01A100

Mfr. #:
Buy S1V30120F01A100
Manufacturer:
Epson ICs
Description:
Audio DSPs Text-to-Speech Audio Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet