S1V30120F01A100 Datasheet S1V30120F01A100 | P7-P9

4. Pin Description

4 EPSON S1V30120 Hardware Specification (Rev. 1.2)

Full-digital audio amplifier

Pin Name Pin I/O

I/O Cell

Type

RESET#

State

Power Pin Description

HPO 26 O LOT L AVDD Audio output

HPON 17 O O1 L HVDD Inverted, unbuffered –digital- version of

HPO

AUDCLK 22 O O1 L HVDD Audio PWM clock

HPOP 21 O O1 H HVDD Unbuffered –digital- version of HPO

SPPDN 31 O O1 L HVDD Open in normal operation

SPHMT 30 O O1 L HVDD Audio output in output period (Low active)

Clock/Reset

Pin Name Pin I/O

I/O Cell

Type

RESET#

State

Power Pin Description

CLKI 36 I IC Z HVDD Reference clock input (32.768kHz）

NRESET 62 I IH Z HVDD Reset input (Low active)

Test

Pin Name Pin I/O

I/O Cell

Type

RESET#

State

Power Pin Description

TSTMODE[2:0]

44,

43,

I IC Z HVDD Test pin (Set to low in normal operation)

TESTEN 40 I ITST1 Pull-down LVDD Test pin (Set to low in normal operation)

SCANEN 63 I IBD2 Pull-down HVDD Test pin (Set to low in normal operation)

EXCKM 38 I IC Z HVDD Test pin (Set to low in normal operation)

NTRST 15 I IH Z HVDD Test pin (Set to low in normal operation)

TDI 14 I ICP1 Pull-up HVDD Test pin (Set to high in normal operation)

TMS 13 I ICP1 Pull-up HVDD Test pin (Set to high in normal operation)

TCK 12 I ICP1 Pull-up HVDD Test pin (Set to high in normal operation)

TDO 19 O T1 Z HVDD Test pin (Open in normal operation)

VCP 34 O LOT Z PLLVDD Test pin (Open in normal operation)

Power supply

Pin Name Pin I/O Pin Description

HVDD 8,18,28,37,49,56,64 P Power supply for I/O buffers (3.3V)

LVDD 3,11,20,24,29,39,45,50,57 P Power supply for the internal circuit (1.8V)

PLLVDD 33 P Power supply for PLL (1.8V)

AVDD 27 P Power supply for full-digital amplifier (1.8V /

3.3V)

VSS 6,16,23,32,41,51,61 P GND (I/O, internal circuit)

PLLVSS 35 P GND (PLL)

AVSS 25 P GND (Full-digital amplifier)

5. Function Description

S1V30120 Hardware Specification (Rev. 1.2) EPSON 5

5. Function Description

5.1 Typical Application System

Mono

3.3V / 1.8V

32.768 KHz

HOST

Host Message I/F

(Serial interface)

S1V30120

FLASH

(SRAM_VECTORS)

Fig. 5-1 Standard Application system

Fig. 5-1 illustrates a typical application system using the S1V30120. The host processor

communicates with the S1V30120 over the serial interface, using commands (message protocol) to

control the embedded algorithms. For more information on commands, see “S1V30120 Message

Protocol Specification.”

On reset the S1V30120 runs the bootstrap loader firmware. The host must then use bootstrap loader

messages to load the SRAM firmware contents and ROM firmware updates (SRAM_VECTORS)

into the S1V30120 device’s SRAM and to switch to running the main mode. These

SRAM_VECTORS are stored in FLASH in the typical application system shown in Fig. 5-1 above.

Refer to section 4 of the S1V30120 message protocol specification for details of the bootstrap loader

messages and section 5 for details of the the main mode messages.

6. Electrical Characteristics

6 EPSON S1V30120 Hardware Specification (Rev. 1.2)

6. Electrical Characteristics

6.1 Absolute Maximum Rating

(VSS=0[V])

Parameter Symbol Rated Value Unit

HVDD VSS-0.3 ~+4.0 V

LVDD VSS-0.3~+2.5 V

PLLVDD VSS-0.3 ~ +2.5 V

Supply voltage

AVDD VSS-0.3 ~ +4.0 V

HVI VSS-0.3 ~ HVDD+0.5 V Input voltage

LVI VSS-0.3 ~ LVDD+0.5 V

HVO VSS-0.3 ~ HVDD+0.5 V Output voltage

AVO VSS-0.3 ~ HVDD+0.5 V

Output current/pin

(Except HPO)

IOUT ±10 mA

Storage temperature Tstg -65 ~ +150 °C

6.2 Recommended Operating Conditions

(VSS=0[V])

Parameter Symbols Min. Typ. Max. Unit

HVDD 3.00 3.30 3.60 V

LVDD 1.65 1.80 1.95 V

PLLVDD 1.65 1.80 1.95 V

1.65 1.80 1.95

Supply voltage

AVDD

3.00 3.30 3.60

HVI VSS - HVDD V Input voltage

LVI VSS - LVDD V

Ambient temperature Ta -40 25 85 °C

Take the following sequences for powering on or off the IC:

(When AVDD=1.8V)

Power on: LVDD/PLLVDD/AVDD => HVDD

Power off: HVDD => LVDD/PLLVDD/AVDD

(When AVDD=3.3V)

Power on: LVDD/PLLVDD => HVDD/AVDD

Power off: HVDD/AVDD => LVDD/PLLVDD

Notes:

− Do not apply voltage only to HVDD longer than a second with LVDD, PLLVDD and AVDD

turned off, or the product reliability may be harmed.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

S1V30120F01A100

Mfr. #:

Buy S1V30120F01A100

Manufacturer:

Epson ICs

Description:

Audio DSPs Text-to-Speech Audio Processor

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

S1V30120F01A100