LTC3879
19
3879f
Other losses, which include the C
OUT
ESR loss, bottom
MOSFET reverse recovery loss and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve effi ciency, the input
current is the best indicator of changes in effi ciency. If you
make a change and the input current decreases, then the
effi ciency has increased. If there is no change in input
current there is no change in effi ciency.
Checking Transient Response
The regulator loop response can be checked by look-
ing at the load transient response. Switching regulators
take several cycles to respond to a step in load current.
When a load step occurs, V
OUT
immediately shifts by an
amount equal to ΔI
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
. ΔI
LOAD
also begins to charge
or discharge C
OUT
, generating a feedback error signal
used by the regulator to return V
OUT
to its steady-state
value. During this recovery time, V
OUT
can be monitored
for overshoot or ringing that would indicate a stability
problem. The I
TH
pin external components shown in the
Design Example will provide adequate compensation for
most applications.
A rough compensation check can be made by calculating
the gain crossover frequency, f
GCO
. g
m(EA)
is the error
amplifi er transconductance, R
C
is the compensation re-
sistor and feedback divider attenuation is assumed to be
0.6V/V
OUT
. This equation assumes that no feed-forward
compensation is used on feedback and that C
OUT
sets the
dominant output pole.
fg R
I
CV
GCO m EA C
LIMIT
OUT OUT
=
()
••
.
•
••
•
.
16
1
2
06
π
As a rule of thumb the gain crossover frequency should be
less than 20% of the switching frequency. For a detailed
explanation of switching control loop theory see Applica-
tion Note 76.
High Switching Frequency Operation
Special care should be taken when operating at switch-
ing frequencies greater than 800kHz. At high switching
frequencies there may be an increased sensitivity to
PCB noise which may result in off-time variation greater
than normal. This off-time instability can be prevented
in several ways. First, carefully follow the recommended
layout techniques. Second, use 2μF or more of X5R or
X7R ceramic input capacitance per Amp of load current.
Third, if necessary, increase the bottom MOSFET ripple
voltage to 30mV
P-P
or greater. This ripple voltage is equal
to R
DS(ON)
typical at 25°C • I
P-P
.
Design Example
Figure 10 is a power supply design example with the fol-
lowing specifi cations: V
IN
= 4.5V to 28V (12V nominal),
V
OUT
= 1.2V ±5%, I
OUT(MAX)
= 15A and f = 400kHz. Start
by calculating the timing resistor, R
ON
:
R
V
VkHzpF
k
ON
==
12
0 7 400 10
429
.
.• •
Select the nearest standard resistor value of 432k for a
nominal operating frequency of 396kHz. Set the inductor
value to give 35% ripple current at maximum V
IN
using
the adjusted operating frequency:
L
V
kHz A
μH=
⎛
⎝
⎜
⎞
⎠
⎟
=
12
396 0 35 15
1
12
28
055
.
•. •
–
.
.
Select 0.56μH which is the nearest value.
The resulting maximum ripple current is:
ΔI
V
kHz μH
V
V
A
L
=
⎛
⎝
⎜
⎞
⎠
⎟
=
12
396 0 56
1
12
28
51
.
•.
–
.
.
Choose the synchronous bottom MOSFET switch and
calculate the V
RNG
current limit set-point. To calculate
V
RNG
and V
DS
, the ρτ term normalization factor (unity
APPLICATIONS INFORMATION
