Page 10 ams Datasheet
Document Feedback [v1-10] 2018-Mar-08
TCS3430 − Register Description
Figure 13:
Register Overview
Note(s):
1. Register Access:
R = Read Only
W = Write Only
R/W = Read or Write
SC = Self Clearing after access
Address Register Name R/W Register Function Reset Value
0x80 ENABLE R/W Enables states and interrupts 0x00
0x81 ATIME R/W ADC integration time 0x00
0x83 WTIME R/W ALS wait time 0x00
0x84 AILTL R/W ALS interrupt low threshold low byte 0x00
0x85 AILTH R/W ALS interrupt low threshold high byte 0x00
0x86 AIHTL R/W ALS interrupt high threshold low byte 0x00
0x87 AIHTH R/W ALS interrupt high threshold high byte 0x00
0x8C PERS R/W ALS interrupt persistence filters 0x00
0x8D CFG0 R/W Configuration register zero 0x80
0x90 CFG1 R/W Configuration register one 0x00
0x91 REVID R Revision ID 0x41
0x92 ID R Device ID 0xDC
0x93 STATUS R Device status register one 0x00
0x94 CH0DATAL R Z CH0 ADC Low Byte Register 0x00
0x95 CH0DATAH R Z CH0 ADC High Byte Register 0x00
0x96 CH1DATAL R Y Ch1 ADC Low Byte Register 0x00
0x9
7
CH1DATAH R Y CH1 ADC High Byte Register 0x00
0
x
98
CH2DATAL R IR1 - CH2 ADC Low Byte Register 0x00
0
x
99
CH2DATAH R
IR1 - Ch2 ADC High Byte Register
0x00
0x9
A
CH3DATAL R X or IR2 - CH3 ADC Low Byte Register 0x00
0
x
9
B
CH3DATAH R X or IR2 - CH3 ADC High Byte Register 0x00
0
x
9
FCF
G
2
R
/
W
Configuration
re
gi
s
t
e
r
t
w
o
0x04
0xAB CFG3
R
/W
Configuration register three 0x00
0xD6 AZ_CONFIG
R
/
W
Auto zero configuration 0x7F
0xDD INTENAB
R
/W
Interrupt enables 0x00
