Page 14 ams Datasheet
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TCS3430 − Register Description
AILTH Register (0x85)
Figure 18:
AILTH Register
This register provides the high byte of the low interrupt ALS
(Channel 0) threshold.
The contents of the AILTH and AILTL registers are combined and
treated as a sixteen bit threshold. If the value generated by
Channel 0 is below the low threshold specified and the APERS
value is reached, the aint bit is asserted which will assert the
INT pin if aien is set.
There is an 8-bit data latch implemented that stores the written
low byte until the high byte is written. Both bytes will be applied
then at the same time to avoid an invalid threshold (e.g. when
going from 0x00ff to 0x0100, the invalid intermediate value
0x0000 is suppressed. This implies that 1) the LSB cannot be
changed without writing to the MSB and 2) that writing to the
LSB of one 16-bit value and afterwards to the MSB of another
16-bit register will write all 16 bits to the MSB related register.
0x85: AILTH
Field Name Reset Type Description
7:0 AILTH 0x00 RW High Byte of the Low Threshold
