AD7680
Rev. A | Page 17 of 24
SERIAL INTERFACE
Figure 20 shows the detailed timing diagram for serial
interfacing to the AD7680. The serial clock provides the
conversion clock and also controls the transfer of information
from the AD7680 during conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track-and-hold into hold mode,
takes the bus out of three-state, and samples the analog input.
The conversion is also initiated at this point and requires at least
20 SCLK cycles to complete. Once 17 SCLK falling edges have
elapsed, the track-and-hold goes back into track mode on the
next SCLK rising edge. Figure 20 shows a 24 SCLK transfer that
allows a 100 kSPS throughput rate. On the 24th SCLK falling
edge, the SDATA line goes back into three-state. If the rising
edge of
CS
occurs before 24 SCLKs have elapsed, the conversion
terminates and the SDATA line goes back into three-state;
otherwise SDATA returns to three-state on the 24th SCLK
falling edge as shown in Figure 20.
A minimum of 20 serial clock cycles are required to perform
the conversion process and to access data from the AD7680.
CS
going low provides the first leading zero to be read in by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges beginning with the second
leading zero; thus the first falling clock edge on the serial clock
has the first leading zero provided and also clocks out the
second leading zero. If a 24 SCLK transfer is used as in Figure 20,
the data transfer consists of four leading zeros followed by the
16 bits of data, followed by four trailing zeros. The final bit
(fourth trailing zero) in the data transfer is valid on the 24th
falling edge, having been clocked out on the previous (23rd)
falling edge. If a 20 SCLK transfer is used as shown in Figure 21,
the data output stream consists of only four leading zeros
followed by 16 bits of data with the final bit valid on the 20th
SCLK falling edge. A 20 SCLK transfer allows for a shorter cycle
time and therefore a faster throughput rate is achieved.
03643-0-013
t
QUIET
t
CONVERT
t
1
t
8
t
7
t
5
t
6
t
3
t
4
4 LEADING ZEROS
3-STATE 3-STATE
0 ZERO ZERO ZERO DB15 DB1 DB0 ZERO ZERO ZERO ZERO
SCLK
1234518192021222324
SDATA
4 TRAILING ZEROS
CS
t
2
Figure 20. AD7680 Serial Interface Timing Diagram—24 SCLK Transfer
03643-0-014
t
QUIET
t
6
t
5
t
7
t
8
t
4
t
3
t
CONVERT
t
2
t
1
0 0ZERO ZERO ZERO DB15 DB1 DB0
SCLK
12345181920
SDATA
CS
4 LEADING ZEROS
3-STATE3-STATE
Figure 21. AD7680 Serial Interface Timing Diagram—20 SCLK Transfer
