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AD7680ARMZ

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AD7680
Rev. A | Page 6 of 24
TIMING SPECIFICATIONS
1
Table 4. V
DD
= 2.5 V to 5.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Limit at T
MIN
, T
MAX
Parameter 3 V 5 V Unit Description
f
SCLK
2
250 250 kHz min
2.5 2.5 MHz max
t
CONVERT
20 × t
SCLK
20 × t
SCLK
min
t
QUIET
100 100 ns min Minimum quiet time required between bus relinquish and start of next conversion
t
1
10 10 ns min
Minimum
CS
pulse width
t
2
10 10 ns min
CS
to SCLK setup time
t
3
3
48 35 ns max
Delay from
CS
until SDATA three-state disabled
t
4
3
120 80 ns max Data access time after SCLK falling edge
t
5
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK low pulse width
t
6
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK high pulse width
t
7
10 10 ns min SCLK to data valid hold time
t
8
4
45 35 ns max SCLK falling edge to SDATA high impedance
t
POWER-UP
5
1 1 μs typ Power up time from full power-down
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t
8
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
5
See Power vs. Throughput Rate section.
03643-0-002
200μAI
OL
200μAI
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
Figure 2. Load Circuit for Digital Output Timing Specification
AD7680
Rev. A | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 5. T
A
= 25°C, unless otherwise noted.
Parameter Rating
V
DD
to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to GND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to V
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
1
±10 mA
Operating Temperature Range
Commercial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
SOT-23 Package, Power Dissipation 450 mW
θ
JA
Thermal Impedance 229.6°C/W
θ
JC
Thermal Impedance 91.99°C/W
MSOP Package, Power Dissipation 450 mW
θ
JA
Thermal Impedance 205.9°C/W
θ
JC
Thermal Impedance 43.74°C/W
Lead Temperature, Soldering
Vapor Phase (60 secs) 215°C
Infared (15 secs) 220°C
ESD 2 kV
1
Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD7680
Rev. A | Page 8 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
03643-0-003
CS
SDATA
SCLK
6
5
4
V
DD
1
GND
2
V
IN
3
AD7680
TOP VIEW
(Not to Scale)
SOT-23
Figure 3. SOT-23 Pin Configuration
03643-0-022
NC = NO CONNECT
AD7680
MSOP
TOP VIEW
(Not to Scale)
V
DD
1
GND
2
GND
3
V
IN
4
CS
SDATA
NC
SCLK
8
7
6
5
Figure 4. MSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
SOT-23
Pin No.
MSOP Mnemonic Function
1 1 V
DD
Power Supply Input. The V
DD
range for the AD7680 is from 2.5 V to 5.5 V.
2 2, 3 GND
Analog Ground. Ground reference point for all circuitry on the AD7680. All analog input signals should
be referred to this GND voltage.
3 4 V
IN
Analog Input. Single-ended analog input channel. The input range is 0 V to V
DD
.
4 5 SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from this part. This clock
input is also used as the clock source for the AD7680's conversion process.
5 7 SDATA
Data Out. Logic output. The conversion result from the AD7680 is provided on this output as a serial
data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the
AD7680 consists of four leading zeros followed by 16 bits of conversion data that are provided MSB
first. This will be followed by four trailing zeroes if
CS
is held low for a total of 24 SCLK cycles. See the
section. Serial Interface
6 8
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7680 and framing the serial data transfer.
N/A 6 NC No Connect. This pin should be left unconnected.
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AD7680ARMZ

Mfr. #:
Buy AD7680ARMZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3mW 100kSPS 16-Bit
Lifecycle:
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