LTC1922-1
11
OPERATIO
U
Adaptive Mode
The LTC1922-1 is configured for adaptive delay sensing
with three pins, ADLY, PDLY and SBUS. ADLY and PDLY
sense the active and passive delay legs respectively via a
voltage divider network as shown in Figure 2.
Zero Voltage Switching (ZVS)
A lossless switching transition requires that the respective
full-bridge MOSFETs be switched to the “ON” state at the
exact instant their drain to source voltage is zero. Delaying
the turn-on results in lower efficiency due to circulating
current flowing in the body diode of the primary side
MOSFET rather than its low resistance channel. Premature
turn-on produces hard switching of the MOSFETs, in-
creasing noise and power dissipation. Previous solutions
have attempted to meet these requirements with fixed or
first order (linear) variable open-loop time delays. Open-
loop methods typically set the turn-on delay to the worst
case longest bridge transition time expected plus the
tolerances of all the internal and external delay timing
circuitry. These error tolerances can be quite significant,
while the optimal transition times over the load current
range vary nonlinearly. In a volume production environ-
ment, these factors can necessitate an external trim to
guarantee ZVS operation, adding cost to the final product.
An additional side effect of longer than required delays is
a decrease in the effective maximum duty cycle. Reduced
duty cycle range can mandate a lower transformer turns
ratio, impacting efficiency or requiring a lower switching
frequency, impacting size.
LTC1922-1 Adaptive Delay Circuitry
The LTC1922-1 addresses the issue of nonideal switching
delays with novel DirectSense circuitry that intelligently
monitors both the input supply and instantaneous bridge
leg voltages, and commands a switching transition when
the expected zero voltage condition is reached. In effect,
the LTC1922-1 “closes the loop” on the ZVS turn-on delay
requirements. DirectSense technology provides optimal
turn-on delay timing, regardless of input voltage, output
load, or component tolerances and greatly simplifies the
power supply design process. The DirectSense technique
requires only a simple voltage divider sense network to
implement. If there is not enough energy to fully commu-
tate the bridge leg to a ZVS condition, the LTC1922-1
automatically overrides the DirectSense circuitry and forces
a transition. The LTC1922-1 delay circuitry can also be
overridden, by tying SBUS to V
REF
.
SBUS
ADLY
PDLY
R2
R5
R6
R1
R3
1k
R4
1k
R
CS
A
B
C
D
V
IN
1922 F02
Figure 2. Adaptive Mode
The threshold voltage on PDLY and ADLY for both the
rising and falling transitions is set by the voltage on SBUS.
A buffered version of this voltage is used as the threshold
level for the internal DirectSense circuitry. At nominal V
IN
,
the voltage on SBUS is set to 1.5V by an external voltage
divider between V
IN
and GND, making this voltage directly
proportional to V
IN
. The LTC1922-1 DirectSense circuitry
uses this characteristic to zero voltage switch all of the
external power MOSFETs, independent of input voltage.
ADLY and PDLY are connected through voltage dividers to
the active and passive bridge legs respectively. The lower
resistor in the divider is set to 1k. The upper resistor in the
divider is divided into one, two or three equal value
resistors to reduce its overall capacitance. In off-line
applications, this is usually required anyway to stay within
the maximum voltage ratings of the resistors. One or two
resistor segments will work for most nominal 48V or lower
V
IN
applications.
To set up the ADLY and PDLY resistors, first determine at
what drain to source voltage to turn-on the MOSFETs.
Finite delays exist between the time at which the LTC1922-1
controller output transitions, to the time at which the
power MOSFET switches on due to MOSFET turn on delay
and external driver circuit delay. Ideally, we want the
power MOSFET to switch at the instant there is zero volts
across it. By setting a threshold voltage for ADLY and
