MT9122 Data Sheet
11
Zarlink Semiconductor Inc.
Controller Mode
The echo canceller functions are selected in Control Register 1 and Control Register 2 through four control bits:
MuteS, MuteR, Bypass and AdaptDis. See Register Summary for details.
MT9122 Throughput Delay
The throughput delay of the MT9122 varies according to the data path and the device configuration. For all device
configurations, except for Bypass state, Rin to Rout has a delay of two frames and Sin to Sout has a delay of three
frames. In Bypass state, the Rin to Rout and Sin to Sout paths have a delay of two frames. In ST-BUS operation,
the D and C channels have a delay of one frame.
Power Down
Forcing the PWRDN
pin to logic low, will put the MT9122 into a power down state. In this state all internal clocks are
halted, the DATA1, Sout and Rout pins are tristated and the F0od
, TD1, and TD2 pins output high.
The device will automatically begin the execution of its initialization routines when the PWRDN
pin is returned to
logic high and a clock is applied to the MCLK pin. The initialization routines execute for one frame and will set the
MT9122 to default register values.
Device Configuration
The MT9122 architecture contains two individually controlled echo cancellers (Echo Canceller A and B). They can
be set in three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figure 3.
Normal Configuration:
In this configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in
Figure 3a, providing 64 milliseconds of echo cancellation in two channels simultaneously.
In SSI operation, both channels are available in different timeslots on the same TDM (Time Division Multiplexing)
bus. For Echo Canceller A, the ENA1 enable strobe pin defines the Rin/Sout (PORT1) time slot while the ENA2
enable strobe pin defines the Sin/Rout (PORT2) time slot. The ENB1 and ENB2 enable strobes perform the same
function for Echo Canceller B.
In ST-BUS operation, the ENA1, ENA2, ENB1 and ENB2 pins are used to determine the PCM data format and the
channel locations. See Table 4.
Back-to-Back Configuration:
In this configuration, the two echo cancellers are positioned to cancel echo coming from both directions in a single
channel providing full duplex 64 millisecond echo-cancellation. See Figure 3c. This configuration uses only one
timeslot on PORT1 and PORT2, allowing a no-glue interface for applications where bidirectional echo cancellation
is required.
In SSI operation, ENA1 and ENA2 enable pins are used to strobe data on Rin/Sout and Sin/Rout respectively. In
ST-BUS operation, ENA1, ENA2, ENB1 and ENB2 inputs are used to select the ST-BUS mode according to Table
4.
Examples of Back-to-Back configuration include positioning the MT9122 between a codec and a transmission
device or between two codecs for echo control on analog trunks.
Extended Delay Configuration:
In this configuration, the two echo cancellers are internally cascaded into one 128 millisecond echo canceller. See
Figure 3b. In SSI operation, ENA1 and ENA2 enable pins are used to strobe data on Rin/Sout and Sin/Rout
