MT9122 Data Sheet
5
Zarlink Semiconductor Inc.
Notes:
1. All unused inputs should be connected to logic low or high unless otherwise stated. All outputs should be left open circuit when not used.
2. All inputs have TTL compatible logic levels except for MCLK, Sin and Rin pins which have CMOS compatible logic levels and PWRDN
pin
which has Schmitt trigger compatible logic levels.
3. All outputs are CMOS pins with CMOS logic levels.
Functional Description
The MT9122 architecture contains two individually controlled echo cancellers (Echo Canceller A and B). They can
be set in three distinct configurations: Normal, Back-to-Back and Extended Delay (see Figure 3). Under Normal
configuration, the two echo cancellers are positioned in parallel providing 64 millisecond echo cancellation in two
channels simultaneously. In Back-to-Back configuration, the two echo cancellers are positioned to cancel echo
coming from both directions in a single channel. In Extended-Delay configuration, the two echo cancellers are
internally cascaded into one 128 millisecond echo canceller.
Each echo canceller contains the following main elements (see Figure 1).
• Adaptive Filter for estimating the echo channel
• Subtracter for cancelling the echo
• Double-Talk detector for disabling the filter adaptation during periods of double-talk
• Non-Linear Processor for suppression of residual echo
• Disable Tone Detectors for detecting valid disable tones at the input of receive and send paths
• Narrow-Band Detector for preventing Adaptive Filter divergence caused by narrow-band signals
• Offset Null filters for removing the DC component in PCM channels
• 12dB attenuator for signal attenuation
• Serial controller interface compatible with Motorola, National and Intel microcontrollers
• PCM encoder/decoder compatible with µ/A-Law ITU-T G.711, µ/A-Law Sign-Mag or linear 2’s complement
coding
The MT9122 has two modes of operation: Controllerless and Controller. Controllerless mode is intended for
applications where customization is not required. Controller mode allows access to all registers for customizing the
MT9122 operation. Refer to Table 7 for a complete list. Controller mode is selected when CONFIG1 and CONFIG2
pins are both connected to Vss.
Each echo canceller in the MT9122 has four functional states: Mute, Bypass, Disable Adaptation and Enable
Adaptation. These are explained in the section entitled Echo Canceller Functional States.
26 BCLK/C4i
Bit Clock/ST-BUS Clock (Input):
In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit clock. This clock must be
synchronous with ENA1, ENA2, ENB1 and ENB2 enable strobes.
In ST-BUS operation, C4i
pin must be connected to the 4.096 MHz (C4) system clock.
27/28 CONFIG1/
CONFIG2
Device Configuration Pins (Inputs).
When CONFIG1 and CONFIG2 pins are both logic 0, the MT9122 serial microport is enabled.
This configuration is defined as Controller Mode
. When CONFIG1 and CONFIG2 pins are in
any other logic combination, the MT9122 is configured in Controllerless Mode
. See Table 3.
Pin Description (continued)
Pin # Name Description
