MT9122 Data Sheet
15
Zarlink Semiconductor Inc.
information detailing whether the second byte transfer will be a read or a write operation and at what address. The
next 8 clock cycles are used to transfer the data byte between the MT9122 and the microcontroller. At the end of
the two-byte transfer, CS
is brought high again to terminate the session. The rising edge of CS will tri-state the
DATA1 pin. The DATA1 pin will remain tri-stated as long as CS
is high.
Intel processors utilize Least Significant Bit (LSB) first transmission while Motorola/National processors use Most
Significant Bit (MSB) first transmission. The MT9122 microport automatically accommodates these two schemes
for normal data bytes. However, to ensure timely decoding of the R/W
and address information, the
Command/Address byte is defined differently for Intel and Motorola/National operations. Refer to the relative timing
diagrams of Figures 10 and 11.
Receive data is sampled on the rising edge of SCLK while transmit data is clocked out on the falling edge of SCLK.
Detailed microport timing is shown in Figure 19 and Figure 20.
Function Controllerless
selected when pins CONFIG1 & 2 ≠ 00
Controller
selected when pins CONFIG1 & 2 = 00
Normal Configuration Set pins CONFIG1 to 1 and CONFIG2 1 to select this
configuration.
Set bits Extended-Delay to 0 and BBM to 0 in Control Reg-
ister 1 to select.
Back-to-Back
Configuration
Set pins CONFIG1 to 1 and CONFIG2 to 0 to select
this configuration.
Set bit BBM to 1 in Control Register 1 to select.
Extended Delay
Configuration
Set pins CONFIG1 to 0 and CONFIG2 to 1 to select
this configuration.
Set bit Extended-Delay to 1 in Control Register 1 to select.
Mute Set pins S2/S1 to 00 and S4/S3 to 00 to select for Echo
Canceller A and Echo Canceller B respectively.
Set bit MuteR to 1 or MuteS to 1 in Control Register 2 to
select.
Bypass Set pins S2/S1 to 01 and S4/S3 to 01 to select for Echo
Canceller A and Echo Canceller B, respectively.
Set bit Bypass to 1 in Control Register 1 to select.
Disable Adaptation Set pins S2/S1 to 10 and S4/S3 to 10 to select for Echo
Canceller A and Echo Canceller B, respectively.
Set bit AdaptDis to 1 in Control Register 1 to select.
Enable Adaptation Set pins S2/S1 to 11 and S4/S3 to 11 to select for Echo
Canceller A and Echo Canceller B, respectively.
Set bits AdaptDis to 0 and Bypass to 0 in Control Register
1 to select.
SSI Tie pin F0i
to VSS to select. Tie pin F0i to VSS to select.
ST-BUS Apply a valid ST-BUS frame pulse to F0i
pin to select. Apply a valid ST-BUS frame pulse to F0i pin to select.
12dB Attenuator Always disabled. Set bit PAD to 1 in Control Register 1 to enable.
Double-Talk
Detector
Continuously enabled which disables filter adaptation
when double-talk is detected.
The detection threshold can be controlled via Double-Talk
Detection Threshold Register 1 and 2.
Disable Tone
Detector
It is continuously enabled and puts TD1
or TD2 or both
into active low when disable tone is detected. The TD1
and TD2
outputs have to be externally manipulated by
the user to bypass the echo canceller.
Set bit TDis to 1 in Control Register 2 to disable tone
detectors.
Disable Tone Set pin REV to 1 to select disable tone with phase
reversal (G.165).
Set bit PHDis to 1 in Control Register 2 to select disable
tone without phase reversal (G164).
Non-Linear
Processor
Set pin NLP to 1 to enable. Set bit NLPDis to 1 to disable.
PCM Law Set pin LAW to 1 or 0 to select A-Law or µ-Law
respectively.
Set pin LAW to 1or 0 to select A-Law or µ-Law
respectively.
PCM Format Set pin FORMAT to 0 or 1 to select Sign-Magnitude or
ITU-T format respectively.
Set pin FORMAT to 0 or 1 to select Sign-Magnitude or
ITU-T format respectively.
Narrow-Band Signal
Detector
Continuously enabled which disables the filter adapta-
tion when narrow band signal is detected.
Set bit NBDis to 1 in Control Register 2 to disable.
Table 7 - MT9122 Function Control Summary
