DS636F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 19
EP9301
Entry Level ARM9 System-on-Chip Processor
Static Memory 32-bit Write on 8-bit External Bus
Parameter Symbol Min Typ Max Unit
AD setup to WRn assert time
t
ADs
t
HCLK
3-
-ns
WRn/DQMn deassert to AD transition time
t
ADd
--
t
HCLK
+ 6
ns
AD hold from WRn deassert time
t
ADh
t
HCLK
× 2
--ns
CSn hold from WRn deassert time
t
CSh
7--ns
CSn to WRn assert delay time
t
WRd
--2ns
WRn assert time
t
WRpwL
-
t
HCLK
× (WST1 + 1)
-ns
WRn deassert time
t
WRpwH
-
t
HCLK
× 2(t
HCLK
× 2) + 14
ns
CSn to DQMn assert delay time
t
DQMd
--1ns
DQMn assert time
t
DQMpwL
-
t
HCLK
× (WST1 + 1)
-ns
DQMn deassert time
t
DQMpwH
--
(t
HCLK
× 2) + 7
ns
WRn / DQMn deassert to DA transition time
t
DAh
t
HCLK
-
-ns
WRn / DQMn assert to DA valid time
t
DAV
--8ns
Figure 7. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement
20 Copyright 2010 Cirrus Logic (All Rights Reserved) DS636F2
EP9301
Entry Level ARM9 System-on-Chip Processor
Static Memory 32-bit Read on 16-bit External Bus
Parameter Symbol Min Typ Max Unit
AD setup to CSn assert time
t
ADs
t
HCLK
-
-ns
CSn assert to AD transition time
t
ADd1
-
t
HCLK
× (WST1 + 1)
-ns
AD transition to CSn deassert time
t
ADd2
-
t
HCLK
× (WST1 + 2)
-ns
AD hold from CSn deassert time
t
ADh
t
HCLK
--ns
RDn assert time
t
RDpwL
-
t
HCLK
× ((2 × WST1) + 3)
-ns
CSn to RDn delay time
t
RDd
--3ns
CSn assert to DQMn assert delay time
t
DQMd
--1ns
DA setup to AD transition time
t
DAs1
15 - - ns
DA to RDn deassert time
t
DAs2
t
HCLK
+ 12
--ns
DA hold from AD transition time
t
DAh1
0--ns
DA hold from RDn deassert time
t
DAh2
0--ns
Figure 8. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement
CSn
WRn
RDn
DA
AD
DQMn
t
RDpwl
t
ADd1
t
RDh
t
DQMh
t
DAh2
t
DAs1
t
DAh1
t
DAs2
WAIT
t
ADs
t
RDd
t
DQMd
t
ADh
t
ADd2
DS636F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 21
EP9301
Entry Level ARM9 System-on-Chip Processor
Static Memory 32-bit Write on 16-bit External Bus
Parameter Symbol Min Typ Max Unit
AD setup to WRn assert time
t
ADs
t
HCLK
– 3 -
-ns
WRn/DQMn deassert to AD transition time
t
ADd
-
-t
HCLK
+ 6
ns
AD hold from WRn deassert time
t
ADh
t
HCLK
× 2 -
-ns
CSn hold from WRn deassert time
t
CSh
7
-
-ns
CSn to WRn assert delay time
t
WRd
--2ns
WRn assert time
t
WRpwL
-
t
HCLK
× (WST1 + 1)
-ns
WRn deassert time
t
WRpwH
--
(t
HCLK
× 2) + 14
ns
CSn to DQMn assert delay time
t
DQMd
--1ns
DQMn assert time
t
DQMpwL
-
t
HCLK
× (WST1 + 1)
-ns
DQMn deassert time
t
DQMpwH
--
(t
HCLK
× 2) + 7
ns
WRn / DQMn deassert to DA transition time
t
DAh1
t
HCLK
-
-ns
WRn / DQMn assert to DA valid time
t
DAV
--
8ns
Figure 9. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement
CSn
WRn
RDn
DQMn
AD
DA
t
ADs
t
WRd
t
WRpwL
t
DAh
t
ADd
t
WRpwH
t
DQMd
t
ADh
t
DAh
t
WRpwL
t
DQpwL
t
DQpwH
t
DQpwL
WAIT
t
CSh
t
DAV
t
DAV

EP9301-IQZ

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Microprocessors - MPU IC Entry-Level ARM9 SOC Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet