OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

EP9301-IQZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
DS636F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 7
EP9301
Entry Level ARM9 System-on-Chip Processor
Ethernet Media Access Controller (MAC)
The MAC subsystem is compliant with the ISO/TEC
802.3 topology for a single shared medium with several
stations. Multiple MII-compliant PHYs are supported.
Features include:
• Supports 1/10/100 Mbps transfer rates for home /
small-business / large-business applications
• Interfaces to an off-chip PHY through industry
standard Media Independent Interface (MII)
Serial Interfaces (SPI, I
2
S, and AC ’97)
The Serial Peripheral Interface (SPI) port can be
configured as a master or a slave, supporting the
National Semiconductor
®
, Motorola
®
, and Texas
Instruments
®
signaling protocols.
The AC'97 port supports multiple codecs for multichannel
audio output with a single stereo input. The I
2
S port
supports stereo 24-bit audio.
These ports are multiplexed so that the I
2
S port will take
over either the AC'97 pins or the SPI pins.
• Normal Mode: One SPI Port and one AC’97 Port
•I
2
S on SSP Mode: One AC’97 Port and one I
2
S Port
•I
2
S on AC’97 Mode: One SPI Port and one I
2
S Port
Note: I
2
S may not be output on AC’97 and SSP ports at the
same time.
12-bit Analog-to-digital Converter (ADC)
The ADC block consists of a 12-bit analog-to-digital
converter with a analog input multiplexer. The multiplexer
can select to measure battery voltage and other
miscellaneous voltages on the external measurement
pins. Features include:
• 5 external pins for ADC measurement
• Measurement pin input range: 0 to 3.3 V.
• ADC-conversion-complete interrupt signal
Table C. Ethernet Media Access Controller Pin Assignments
Pin Mnemonic Pin Description
MDC Management Data Clock
MDIO Management Data I/O
RXCLK Receive Clock
MIIRXD[3:0] Receive Data
RXDVAL Receive Data Valid
RXERR Receive Data Error
TXCLK Transmit Clock
MIITXD[3:0] Transmit Data
TXEN Transmit Enable
TXERR Transmit Error
CRS Carrier Sense
CLD Collision Detect
Table D. Audio Interfaces Pin Assignment
Pin
Name
Normal Mode
I
2
S on SSP
Mode
I
2
S on AC'97
Mode
Pin
Description
Pin Description Pin Description
SCLK1 SPI Bit Clock I2S Serial Clock SPI Bit Clock
SFRM1 SPI Frame Clock I2S Frame Clock SPI Frame Clock
SSPRX1 SPI Serial Input I2S Serial Input SPI Serial Input
SSPTX1
SPI Serial
Output
I2S Serial Output SPI Serial Output
(No I2S Master
Clock)
ARSTn AC'97 Reset AC'97 Reset I2S Master Clock
ABITCLK AC'97 Bit Clock AC'97 Bit Clock I2S Serial Clock
ASYNC
AC'97 Frame
Clock
AC'97 Frame
Clock
I2S Frame Clock
ASDI
AC'97 Serial
Input
AC'97 Serial Input I2S Serial Input
ASDO
AC'97 Serial
Output
AC'97 Serial Output I2S Serial Output
Table E. 12-bit Analog-to-Digital Converter Pin Assignments
Pin Mnemonic Pin Description
ADC[0] (Ym, pin 135) External Analog Measurement Input
ADC[1] (sXp, pin 134) External Analog Measurement Input
ADC[2] (sXm, pin 133) External Analog Measurement Input
ADC[3] (sYp, pin 132) External Analog Measurement Input
ADC[4] (sYm, pin 131) External Analog Measurement Input
8 Copyright 2010 Cirrus Logic (All Rights Reserved) DS636F2
EP9301
Entry Level ARM9 System-on-Chip Processor
Universal Asynchronous
Receiver/Transmitters (UARTs)
Two 16550-compatible UARTs are supplied. One
provides asynchronous HDLC (High-level Data Link
Control) protocol support for full duplex transmit and
receive. The HDLC receiver handles framing, address
matching, CRC checking, control-octet transparency, and
optionally passes the CRC to the host at the end of the
packet. The HDLC transmitter handles framing, CRC
generation, and control-octet transparency. The host
must assemble the frame in memory before
transmission. The HDLC receiver and transmitter use the
UART FIFOs to buffer the data streams. The second
UART provides IrDA
®
compatibility.
• UART1 supports modem bit rates up to 115.2 kbps,
supports HDLC and includes a 16 byte FIFO for
receive and a 16 byte FIFO for transmit. Interrupts are
generated on Rx, Tx and modem status change.
• UART2 contains an IrDA encoder operating at either
the slow (up to 115 kbps), medium (0.576 or 1.152
Mbps), or fast (4 Mbps) IR data rates. It also has a 16
byte FIFO for receive and a 16 byte FIFO for transmit.
Dual Port USB Host
The USB Open Host Controller Interface (Open HCI)
provides full speed serial communications ports at a
baud rate of 12 Mbits/sec. Up to 127 USB devices
(printer, mouse, camera, keyboard, etc.) and USB hubs
can be connected to the USB host in the USB “tiered-
start” topology.
This includes the following feature:
• Compliance with the USB 2.0 specification
• Compliance with the Open HCI Rev 1.0 specification
• Supports both low speed (1.5 Mbps) and full speed
(12 Mbps) USB device connections
• Root HUB integrated with 2 downstream USB ports
• Transceiver buffers integrated, over-current protection
on ports
• Supports power management
• Operates as a master on the bus
The Open HCI host controller initializes the master DMA
transfer with the AHB bus:
• Fetches endpoint descriptors and transfer descriptors
• Accesses endpoint data from system memory
• Accesses the HC communication area
• Writes status and retire transfer descriptor
Note: USBm[1] and USBp[1] are not bonded out.
Two-Wire Interface With EEPROM Support
The two-wire interface provides communication and
control for synchronous-serial-driven devices.
Real-Time Clock with Software Trim
The software trim feature on the real time clock (RTC)
provides software controlled digital compensation of the
32.768 KHz input clock. This compensation is accurate to
± 1.24 sec/month.
Note: A real time clock must be connected to RTCXTALI or
the EP9301device will not boot.
Table F. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Pin Mnemonic Pin Name - Description
TXD0 UART1 Transmit
RXD0 UART1 Receive
CTSn
UART1 Clear To
Send / Transmit Enable
DSRn / DCDn
UART1 Data Set
Ready / Data Carrier Detect
DTRn UART1 Data Terminal Ready
RTSn UART1 Ready To Send
EGPIO[0] / RI UART1 Ring Indicator
TXD1 / SIROUT
UART2 Transmit / IrDA
Output
RXD1 / SIRIN UART2 Receive / IrDA Input
Table G. Dual Port USB Host Pin Assignments
Pin Mnemonic Pin Name - Description
USBp[2,0] USB Positive signals
USBm[2,0] USB Negative Signals
Table H. Two-Wire Port with EEPROM Support Pin Assignments
Pin Mnemonic Pin Name - Description
Alternative
Usage
EECLK Two-wire Interface Clock
General
Purpose I/O
EEDATA Two-wire Interface Data
General
Purpose I/O
Table I. Real-Time Clock with Pin Assignments
Pin Mnemonic Pin Name - Description
RTCXTALI Real-Time Clock Oscillator Input
RTCXTALO Real-Time Clock Oscillator Output
DS636F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 9
EP9301
Entry Level ARM9 System-on-Chip Processor
PLL and Clocking
The Processor and the Peripheral Clocks operate from a
single 14.7456 MHz crystal.
The Real Time Clock operates from a 32.768 KHz
external oscillator.
Timers
The Watchdog Timer ensures proper operation by
requiring periodic attention to prevent a reset-on-time-
out.
Two 16-bit timers operate as free-running down counters
or as periodic timers for fixed-interval interrupts and have
a range of 0.03 ms to 4.27 seconds.
One 32-bit timer, plus a 6-bit prescale counter, has a
range of 0.03 μs to 73.3 hours.
One 40-bit debug timer, plus a 6-bit prescale counter, has
a range of 1.0 μs to 12.7 days.
Interrupt Controller
The interrupt controller allows up to 54 interrupts to
generate an Interrupt Request (IRQ) or Fast Interrupt
Request (FIQ) signal to the processor core. Thirty-two
hardware priority assignments are provided for assisting
IRQ vectoring, and two levels are provided for FIQ
vectoring. This allows time-critical interrupts to be
processed in the shortest time possible. Internal
interrupts may be programmed as active high or active
low level sensitive inputs. GPIO pins programmed as
interrupts may be programmed as active high level
sensitive, active low level sensitive, rising edge triggered,
falling edge triggered, or combined rising/falling edge
triggered.
• Supports 54 interrupts from a variety of sources (such
as UARTs, GPIO and ADC)
• Routes interrupt sources to either the ARM920T’s
IRQ or FIQ (Fast IRQ) inputs
• Three dedicated off-chip interrupt lines INT[2:0]
operate as active-high level-sensitive interrupts
• Any of the 19 GPIO lines maybe configured to
generate interrupts
• Software supported priority mask for all FIQs and
IRQs
Note: INT[2] is not bonded out.
Dual LED Drivers
Two pins are assigned specifically to drive external
LEDs.
General Purpose Input/Output (GPIO)
The 16 EGPIO and the 3 FGPIO pins may each be
configured individually as an output, an input or an
interrupt input.
There are 10 pins that may alternatively be used as input,
output, or open-drain pins, but do not support interrupts.
These pins are:
• Ethernet MDIO
• Both LED Outputs
• EEPROM Clock and Data
• HGPIO[5:2]
• CGPIO[0]
6 pins may alternatively be used as inputs only:
• CTSn, DSRn / DCDn
• 3 Interrupt Lines
2 pins may alternatively be used as outputs only:
•RTSn
•ARSTn
Table J. PLL and Clocking Pin Assignments
Pin Mnemonic Pin Name - Description
XTALI Main Oscillator Input
XTALO Main Oscillator Output
VDD_PLL Main Oscillator Power
GND_PLL Main Oscillator Ground
Table K. External Interrupt Controller Pin Assignment
Pin Mnemonic Pin Name - Description
INT[3] and INT[1:0] External Interrupts 2, 1, 0
Table L. Dual LED Pin Assignments
Pin Mnemonic
Pin Name -
Description
Alternative Usage
GRLED Green LED General Purpose I/O
REDLED Red LED General Purpose I/O
Table M. General Purpose Input/Output Pin Assignment
Pin Mnemonic Pin Name - Description
EGPIO[15:0]
Expanded General Purpose Input / Output
Pins with Interrupts
FGPIO[3:1]
Expanded General Purpose Input / Output
Pins with Interrupts
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

EP9301-IQZ

Mfr. #:
Buy EP9301-IQZ
Manufacturer:
Cirrus Logic
Description:
Microprocessors - MPU IC Entry-Level ARM9 SOC Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet