DS636F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 23
EP9301
Entry Level ARM9 System-on-Chip Processor
Static Memory Burst Write Cycle
Note: These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
Parameter Symbol Min Typ Max Unit
AD setup to WRn assert time
t
ADs
t
HCLK
− 3
ns
AD hold from WRn deassert time
t
ADh
t
HCLK
× 2
ns
WRN/DQMn deassert to AD transition time
t
ADd
t
HCLK
+ 6
ns
CSn hold from WRn deassert time
t
CSh
7
ns
CSn to WRn assert delay time
t
WRd
2ns
CSn to DQMn assert delay time
t
DQMd
1ns
DQMn assert time
t
DQpwL
t
HCLK
× (WST1 + 1)
ns
DQMn deassert time
t
DQpwH
(t
HCLK
× 2) + 14
ns
WRn assert time
t
WRpwL
t
HCLK
× (WST1 + 11)
ns
WRn deassert time
t
WRpwH
(t
HCLK
× 2) + 7
ns
WRn/DQMn deassert to DA transition time
t
DAh
t
HCLK
ns
WRn/DQMn assert to DA valid time
t
DAv
8ns
Figure 11. Static Memory Burst Write Cycle Timing Measurement
AD
CSn
WRn
RD
DQMn
DA
WAIT
t
ADs
t
ADd
t
WRpwL
t
DQpwL
t
DQpwH
t
WRpwH
t
DAv
t
DAh
t
WRd
t
DQMd
t
CSh
t
ADh
