LTC2637
19
2637fb
OPERATION
The LTC2637 is a family of octal voltage output DACs in
14-lead DFN and 16-lead MSOP packages. Each DAC can
operate rail-to-rail using an external reference, or with its
full-scale voltage set by an integrated reference. Eighteen
combinations of accuracy (12-, 10-, and 8-bit), power-on
reset value (zero-scale, mid-scale in internal reference
mode, or mid-scale in external reference mode), and full-
scale voltage (2.5V or 4.096V) are available. The LTC2637
is controlled using a 2-wire I
2
C interface.
Power-On Reset
The LTC2637-HZ/ LTC2637-LZ clear the output to zero-scale
when power is fi rst applied, making system initialization
consistent and repeatable.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2637
contains circuitry to reduce the power-on glitch: the
analog output typically rises less than 5mV above zero-
scale during power on. In general, the glitch amplitude
decreases as the power supply ramp time is increased.
See “Power-On Reset Glitch” in the Typical Performance
Characteristics section.
The LTC2637-HMI/LTC2637-HMX/LTC2637-LMI/
LTC2637-LMX provide an alternative reset, setting the
output to mid-scale when power is fi rst applied. The
LTC2637-LMI and LTC2637-HMI power up in internal
reference mode, with the output set to a mid-scale volt-
age of 1.25V and 2.048V, respectively. The LTC2637-LMX
and LTC2637-HMX power-up in external reference mode,
with the output set to mid-scale of the external reference.
Default reference mode selection is described in the Refer-
ence Modes section.
Power Supply Sequencing
The voltage at REF (Pin 9, DFN; Pin 11, MSOP) must be
kept within the range –0.3V ≤ V
REF
≤ V
CC
+ 0.3V (see
Absolute Maximum Ratings). Particular care should be
taken to observe these limits during power supply turn-
on and turn-off sequences, when the voltage at V
CC
is in
transition.
Transfer Function
The digital-to-analog transfer function is:
V
OUT(IDEAL)
=
k
2
N
⎛
⎝
⎜
⎞
⎠
⎟
V
REF
where k is the decimal equivalent of the binary DAC
input code, N is the resolution, and V
REF
is either 2.5V
(LTC2637-LMI/LTC2637-LMX/LTC2637-LZ) or 4.096V
(LTC2637-HMI/LTC2637-HMX/LTC2637-HZ) when in
Internal Reference mode, and the voltage at REF when in
External Reference mode.
I
2
C Serial Interface
The LTC2637 communicates with a host using the stan-
dard 2-wire I
2
C interface. The timing diagrams (Figures
1 and 2) show the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines. The value of
these pull-up resistors is dependent on the power supply
and can be obtained from the I
2
C specifi cations. For an I
2
C
bus operating in the fast mode, an active pull-up will be
necessary if the bus capacitance is greater than 200pF.
The LTC2637 is a receive-only (slave) device. The master
can write to the LTC2637. The LTC2637 will not acknowl-
edge (NAK) a read request from the master.
START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has fi nished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I
2
C device.
