LTC2637
23
2637fb
OPERATION
command 0111b. In addition, all the DAC channels and
the integrated reference together can be put into power-
down mode using Power Down Chip command 0101b.
When the integrated reference and all DAC channels are
in power-down mode, the REF pin becomes high imped-
ance (typically > 1G). For all power-down commands
the 16-bit data word is ignored.
Normal operation resumes after executing any command
that includes a DAC update, (as shown in Table 1). The
selected DAC is powered up as its voltage output is up-
dated. When a DAC which is in a powered-down state is
powered up and updated, normal settling is delayed. If
less than eight DACs are in a powered-down state prior
to the update command, the power-up delay time is 10µs.
However, if all eight DACs and the integrated reference
are powered down, then the main bias generation circuit
block has been automatically shut down in addition to
the DAC amplifi ers and reference buffers. In this case,
the power up delay time is 12µs. The power-up of the
integrated reference depends on the command that pow-
ered it down. If the reference is powered down using the
Select External Reference Command (0111b), then it can
only be powered back up using Select Internal Reference
Command (0110b). However, if the reference was powered
down using Power Down Chip Command (0101b), then in
addition to Select Internal Reference Command (0110b),
any command that powers up the DACs will also power
up the integrated reference.
Voltage Output
The LTC2637’s DAC output integrated rail-to-rail amplifi ers
have guaranteed load regulation when sourcing or sinking
up to 10mA at 5V, and 5mA at 3V.
Load regulation is a measure of the amplifi er’s ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The amplifi er’s DC output
impedance is 0.1 when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 50 typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage is
50 • 1mA, or 50mV). See the graph “Headroom at Rails
vs. Output Current” in the Typical Performance Charac-
teristics section.
The amplifi er is stable driving capacitive loads of up to
500pF.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is lim-
ited to voltages within the supply range.
Since the analog output of the DAC cannot go below ground,
it may limit for the lowest codes as shown in Figure 5b.
Similarly, limiting can occur near full scale when the REF
pin is tied to V
CC
. If V
REF
= V
CC
and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits
at V
CC
, as shown in Figure 5c. No full-scale limiting can
occur if V
REF
is less than V
CC
–FSE.
Offset and linearity are defi ned and tested over the region
of the DAC transfer function where no output limiting can
occur.
Board Layout
The PC board should have separate areas for the analog and
digital sections of the circuit. A single, solid ground plane
should be used, with analog and digital signals carefully
routed over separate areas of the plane. This keeps digital
signals away from sensitive analog signals and minimizes
the interaction between digital ground currents and the
