256MB, 512MB (x64, DR)
144-PIN SDRAM SODIMM
pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
4 ©2006 Micron Technology, Inc. All rights reserved.
Table 6: Pin Descriptions
Pin numbers may not correlate with symbols; refer to the Pin Assignment tables on page 3 for more information
PIN NUMBERS SYMBOL TYPE DESCRIPTION
65, 66, 67 RAS#, CAS#, WE# Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
61, 74 CK0, CK1 Input
Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
62, 68 CKE0, CKE1 Input
Clock enable: CKE activates (HIGH) and deactivates (LOW) the
CK signal. Deactivating the clock provides PRECHARGE power-
down and SELF REFRESH operation (all device banks idle),
ACTIVE power-down (row ACTIVE in any device bank), or
CLOCK SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and
self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CK,
are disabled during power-down and self refresh modes,
providing low standby power.
69, 71 S0#,S1# Input
Chip select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
23, 24, 25, 26, 115, 116, 117,
118
DQMB0–DQMB7 Input
Input/output mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
106, 110 BA0, BA1 Input
Bank address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
29, 30, 31, 32, 33, 34,
70 (512MB), 103, 104, 105,
109, 111, 112
A0–A11
(256MB)
A0–A12
(512MB)
Input
Address inputs: Provide the row address for ACTIVE commands
and the column address and auto precharge bit (A10) for
READ/WRITE commands, to select one location out of the
memory array in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
142 SCL Input
Serial clock for presence-detect: scl is used to synchronize the
presence-detect data transfer to and from the module.
141 SDA Input/
Output
Serial presence-detect data: sda is a bidirectional pin used to
transfer addresses and data into and data out of the presence-
detect portion of the module.
3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15,
16, 17, 18,19, 20, 37, 38, 39,
40, 41, 42, 43, 44, 47, 48, 49,
50, 51, 52, 53, 54, 83, 84, 85,
86, 87, 88, 89, 90, 93, 94, 95,
96, 97, 98, 99, 100, 121, 122,
123, 124, 125, 126, 127, 128,
131, 132, 133, 134, 135, 136,
137, 138
DQ0–DQ63 Input/
Output
Data I/O: Data bus.
