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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
Features
• Meets jitter requirements of Telcordia GR-253-
CORE for OC-12, OC-3, and OC-1 rates
• Meets jitter requirements of ITU-T G.813 for STM-
4, and STM-1 rates
• Provides one differential LVPECL output clock
selectable to 19.44 MHz, 38.88 MHz, 77.76 MHz,
155.52 MHz, or 622.08 MHz
• Provides a single-ended CMOS output clock at
19.44 MHz
• Accepts a single-ended CMOS reference at
19.44 MHz or a differential LVDS, LVPECL, or
CML reference at 19.44 MHz or 77.76 MHz
• Provides a LOCK indication
• 3.3 V supply
Applications
• SONET/SDH line cards
Description
The ZL30415 is an analog phase-locked loop (APLL)
designed to provide jitter attenuation and rate
conversion for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30415 generates low
jitter output clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-12, OC-3, OC-1 rates
and ITU-T G.813 STM-4 and STM-1 rates.
The ZL30415 accepts a CMOS compatible reference
at 19.44 MHz or a differential LVDS, LVPECL, or CML
reference at 19.44 MHz or 77.76 MHz and generates a
differential LVPECL output clock selectable to
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, or
622.08 MHz, and a single-ended CMOS clock at
19.44 MHz. The ZL30415 provides a lock indication.
September 2006
Ordering Information
ZL30415GGC 64 Ball CABGA Trays
ZL30415GGF 64 Ball CABGA Tape & Reel,
Bake & Drypack
ZL30415GGG2 64 Ball CABGA** Trays, Bake & Drypack
ZL30415GGF2 64 Ball CABGA** Tape & Reel,
Bake & Drypack
**Pb Free Tin/Silver/Copper
-40°C to +85°C
ZL30415
SONET/SDH Clock Multiplier PLL
Data Sheet
Figure 1 - Functional Block Diagram
Frequency
Detector
VCO
Frequency
LPF
OC-CLKoP/N
VCC GND VDD
C19o
FS2
Loop
Filter
BIAS
& Phase
19.44 MHz and 77.76 MHz
State
Machine
LOCK
Reference
Bias Circuit
and
Dividers
and
Clock
Drivers
C19o, C38o, C77o,
C155o, C622o,
LVPECL output
C19i
Reference
Selection
MUX
REF_SEL
REF_FREQ
REFinP/N
C19oEN
C19i or C77i
CML, LVDS,
LVPECL input
03
FS3 FS1
