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ZL30415GGC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
ZL30415 Data Sheet
10
Zarlink Semiconductor Inc.
4.2 Recommended Interface circuit
4.2.1 Interfacing to REFin Receiver
4.2.1.1 Interfacing REFin Receiver to LVPECL Driver
The ZL30415 REFin differential receiver can be connected to LVPECL compatible driver with an interface circuit, as
shown in Figure 8. The R1s and R2s terminating resistors should be placed close to the REFin input balls.
Figure 7 - Interfacing to LVPECL Driver
4.2.1.2 Interfacing REFin Receiver to LVDS or CML Drivers
The ZL30415 REFin differential receiver can be connected to LVDS or CML driver with an interface circuit, as
shown in Figure 8. The 100
Ω
terminating resistors should be placed close to the REFin input balls.
Figure 8 - Interfacing to LVDS or CML Driver
LVPECL
Z=50Ω
Z=50Ω
Typical resistor values: R1 = 127 Ω, R2 = 82.5
Ω
R1
VCC=+3.3 V
R1
Driver
ZL30415
Receiver
Cc
VDD/2
Cc
REFinP
REFinN
R2
R2
ZL30415
Z=50Ω
Driver
Receiver
Z=50Ω
Cc
VDD/2
LVDS
Cc
100Ω
REFinP
REFinN
or
CML
ZL30415 Data Sheet
11
Zarlink Semiconductor Inc.
4.2.2 Interfacing to OC-CLKo Output
4.2.2.1 LVPECL to LVPECL Interface
The OC-CLKo outputs provide differential LVPECL clocks at 622.08 MHz, 155.52 MHz, 77.76 MHz, 38.88 MHz and
19.44 MHz selectable with FS3, FS2 and FS1 frequency select inputs. The LVPECL output drivers require a 50 Ω
termination connected to the Vcc-2V source for each output terminal at the terminating end as shown below. The
terminating resistors should be placed close to the LVPECL receiver.
Figure 9 - LVPECL to LVPECL Interface
LVPECL
LVPECL
ZL30415
Z=50Ω
Z=50Ω
OC-CLKoP
OC-CLKoN
Receiver
GND
Typical resistor values: R1 = 127Ω, R2 =82.5Ω
R1
R2
VCC=+3.3 V
R1
R2
VCC
0.1uF
+3.3 V
Driver
ZL30415 Data Sheet
12
Zarlink Semiconductor Inc.
4.3 Power Supply and BIAS Circuit Filtering Recommendations
Figure 10 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter
performance. The level of required filtering is subject to further optimization and simplification. Please check
Zarlink’s web site for updates.
Figure 10 - Power Supply and BIAS Circuit Filtering
Notes:
1. All the ground pins (GND) are connected to the same ground plane.
2. Select Ferrite Bead with I
DC
> 400 mA and R
DC
in a range from 0.10
Ω
to 0.15
Ω.
B
C
D
E
F
G
H
12345678
1
A
LOCK
VCC2
NC
NC REF_FREQ NC
NC
NC
VDD VDD GND
C19o
VCC
VDD
REF_SEL
GNDGNDVCCVCC
BIAS
GND
GND
REFinP
FS1
FS2
GND
FS3
VCC
GND
C19i
GND
NC
GND GND
OC-CLKoP OC-CLKoN GND
GND
NC
NC VCC1NC NC
GND
LPF
GND
GND GND GND NC
REFinNVDD
VDD
C19oEN
NC NC
VDD
VDD
NC NC NC
NC GND
NC
0.1uF
10uF0.1 uF
Ferrite Bead
33uF
0.1uF
4.7Ω
220Ω
33uF
0.1uF
33uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
+3.3V Power Rail
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

ZL30415GGC

Mfr. #:
Buy ZL30415GGC
Manufacturer:
Microchip / Microsemi
Description:
Phase Locked Loops - PLL SONET / SDH CLOCK MULTIPLIER PLL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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