ZL30415GGC Datasheet ZL30415GGC, ZL30415GGF, ZL30415GGG2 | P4-P6

ZL30415 Data Sheet

Zarlink Semiconductor Inc.

2.0 Functional Description

The ZL30415 is an analog phased-locked loop which provides rate conversion and jitter attenuation for

SONET/SDH OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30415 is shown in

Figure 1 and a brief description is presented in the following sections.

2.1 Reference Selection Multiplexer

The ZL30415 accepts two types of input reference clocks:

- differential: operating at 19.44 MHz or 77.76 MHz, compatible with LVDS/LVPECL/CML threshold levels

- single-ended: operating at 19.44 MHz, compatible with CMOS switching levels.

The REF_SEL input determines whether the single-ended CMOS reference input (REFin) or the differential

reference inputs (REFinP/N) are used as input reference clocks. The REF_FREQ input selects the rate of the

differential input clock to be either 19.44 MHz, or 77.76 MHz. See Table 1 for details.

C19i

C19 Reference Input (CMOS Input). This is a single-ended input reference

source used for synchronization. This input accepts 19.44 MHz.

C19o

Clock 19.44 MHz (CMOS Output). This output provides a single-ended CMOS

clock at 19.44 MHz.

F7, G1 GND Ground. 0 volt

G2 VDD Positive Digital Power Supply. +3.3 V ±10%

G3 REF_SEL Reference Select (CMOS Input). If tied low then the C19i single-ended

reference is used as the input reference source. If tied high then the REFinP/N

differential pair is used as the input reference source.

G4 FS3 See E4 ball description.

G5, G6 GND Ground. 0 volt

G7, G8

VDD

Positive Digital Power Supply. +3.3 V ±10%

H1, H2

No internal bonding Connection. Leave unconnected.

VDD

Positive Digital Power Supply. +3.3 V ±10%

FS1

See E4 ball description.

VDD

Positive Digital Power Supply. +3.3 V ±10%

H7, H8

GND

Ground. 0 volt.

REF_SEL REF_FREQ Selected Input Reference Reference Frequency

0 x C19i 19.44 MHz (CMOS)

1 0 REFin 77.76 MHz (Differential)

1 1 REFin 19.44 MHz (Differential)

Table 1 - Input Reference Selection

Ball Description Table (continued)

Ball # Name Description

ZL30415 Data Sheet

Zarlink Semiconductor Inc.

2.2 Frequency/Phase Detector

The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback

signal from the Frequency Divider circuit and provides an error signal equal to the frequency/phase

difference between the two. This error signal is passed to the Loop Filter circuit.

2.3 Lock Indicator

The ZL30415 has a built-in LOCK detector that measures frequency difference between input reference clock C19i

and the VCO frequency. When the VCO frequency is less than ±300 ppm apart from the input reference frequency

then the LOCK output is set high. The LOCK output is pulled low if the frequency difference exceeds ±1000 ppm.

2.4 Loop Filter

The Loop Filter is a low-pass filter. This low-pass filter eliminates high frequency spectral components from a phase

error signal produced by the Phase Detector. This ensures low output jitter that meets network jitter requirements.

The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF

ball and ground as shown in Figure 3.

Figure 3 - Loop Filter Elements

2.5 VCO

The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the

voltage of the error signal generates a primary frequency. The VCO output is connected to the "Frequency Dividers

and Clock Drivers" block that divides VCO frequency and buffer generated clocks.

ZL30415

LPF

=8.2 k

Ω,

=470 nF

Filter

Loop

Frequency

and Phase

Detector

VCO

ZL30415 Data Sheet

Zarlink Semiconductor Inc.

2.6 Frequency Dividers and Clock Drivers

The output of the VCO feeds the high frequency clock to the "Frequency Dividers and Clock Drivers" circuit to

provide one differential LVPECL compatible clock with selectable frequency and one single-ended 19.44 MHz C19o

output clock. The C19o clock can be enabled or disabled with the associated C19oEN Output Enable ball.

Internally, this block provides a feedback clock that closes the PLL loop.

The frequency of the OC-CLKo differential output clock is selected with FS3, FS2 and FS1 inputs as is shown in the

following table.

FS3 FS2 FS1

OC-CLKo

Frequency

0 0 0 19.44 MHz

0 0 1 38.88 MHz

0 1 0 77.76 MHz

0 1 1 155.52 MHz

1 0 0 622.08 MHz

101Reserved

110Reserved

111Reserved

Table 2 - OC-CLKo Clock Frequency Selection

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

ZL30415GGC

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Buy ZL30415GGC

Manufacturer:

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Description:

Phase Locked Loops - PLL SONET / SDH CLOCK MULTIPLIER PLL

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New from this manufacturer.

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ZL30415GGC

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