ZL30415 Data Sheet
16
Zarlink Semiconductor Inc.
AC Electrical Characteristics
†
- C19i Input to OC-CLKo Output Timing
† Supply voltage and operating temperature are as per Recommended Operating Conditions.
‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.
Figure 14 - C19i Input to OC-CLKo Output Timing
Characteristics Sym. Min. Typ.
‡
Max. Units Notes
1 C19i(CMOS) to C19o(LVPECL) delay t
C19D
1.4 3.3 5.1 ns
2 C19i(CMOS) to OC-CLKo(38) delay t
C38D
1.2 3.0 4.8 ns
3 C19i(CMOS) to OC-CLKo(77) delay t
C77D
0.9 2.6 4.4 ns
4 C19i(CMOS) to OC-CLKo(155) delay t
C155D
0.6 2.3 4.1 ns
5 C19i(CMOS) to OC-CLKo(622) delay t
C622D
00.81.6ns
6 All Output Clock duty cycle d
C
48 50 52 %
OC-CLKo(38)
V
T-LVPECL
C19i
V
T-CMOS
(19.44 MHz)
t
C19D
OC-CLKo(19)
V
T-LVPECL
(19.44 MHz)
t
C38D
(38.88 MHz)
OC-CLKo(155)
V
T-LVPECL
(155.52 MHz)
OC-CLKo(77)
V
T-LVPECL
(77.76 MHz)
t
C77D
t
C155D
Note: All output clocks have nominal 50% duty cycle.
OC-CLKo(622)
V
T-LVPECL
(622.08 MHz)
t
C622D
