P89LPC92X1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2.1 — 27 August 2012 32 of 75
NXP Semiconductors
P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
7.16 I/O ports
The P89LPC9201/9211/922A1/9241/9251 has four I/O ports: Port 0, Port 1 and Port 3.
Ports 0 and 1 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins
available depends upon the clock and reset options chosen, as shown in Table 9
.
7.16.1 Port configurations
All but three I/O port pins on the P89LPC9201/9211/922A1/9241/9251 may be configured
by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional
(standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration
registers for each port select the output type for each port pin.
1. P1.5 (RST
) can only be an input and cannot be configured.
2. P1.2 (SCL/T0) and P1.3 (SDA/INT0
) may only be configured to be either input-only or
open-drain.
7.16.1.1 Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
The P89LPC9201/9211/922A1/9241/9251 is a 3 V device, but the pins are 5 V tolerant. In
quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing
from the pin to V
DD
, causing extra power consumption. Therefore, applying 5 V in
quasi-bidirectional mode is discouraged.
A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
7.16.1.2 Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor
tied to V
DD
.
Table 9. Number of I/O pins available
Clock source Reset option Number of I/O
pins (28-pin
package)
On-chip oscillator or watchdog
oscillator
No external reset (except during
power-up)
18
External RST
pin supported 17
External clock input No external reset (except during
power-up)
17
External RST
pin supported 16
Low/medium/high speed
oscillator (external crystal or
resonator)
No external reset (except during
power-up)
16
External RST pin supported 15
