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P89LPC9241FDH,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75
P89LPC92X1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2.1 — 27 August 2012 49 of 75
NXP Semiconductors
P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
8.5.3 Auto scan, single conversion mode
Any combination of the four input channels can be selected for conversion. A single
conversion of each selected input will be performed and the result placed in the result
register which corresponds to the selected input channel. An interrupt, if enabled, will be
generated after all selected channels have been converted. If only a single channel is
selected this is equivalent to single channel, single conversion mode.
8.5.4 Auto scan, continuous conversion mode
Any combination of the four input channels can be selected for conversion. A conversion
of each selected input will be performed and the result placed in the result register which
corresponds to the selected input channel. An interrupt, if enabled, will be generated after
all selected channels have been converted. The process will repeat starting with the first
selected channel. Additional conversion results will again cycle through the four result
register pairs, overwriting the previous results. Continuous conversions continue until
terminated by the user.
8.5.5 Dual channel, continuous conversion mode
This is a variation of the auto scan continuous conversion mode where conversion occurs
on two user-selectable inputs. The result of the conversion of the first channel is placed in
the result register, AD1DAT0. The result of the conversion of the second channel is placed
in result register, AD1DAT1. The first channel is again converted and its result stored in
AD1DAT2. The second channel is again converted and its result placed in AD1DAT3. An
interrupt is generated, if enabled, after every set of four conversions (two conversions per
channel).
8.5.6 Single step mode
This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any
combination of the four input channels can be selected for conversion. After each channel
is converted, an interrupt is generated, if enabled, and the A/D waits for the next start
condition. May be used with any of the start modes.
8.6 Conversion start modes
8.6.1 Timer triggered start
An A/D conversion is started by the overflow of Timer 0. Once a conversion has started,
additional Timer 0 triggers are ignored until the conversion has completed. The Timer
triggered start mode is available in all ADC operating modes.
8.6.2 Start immediately
Programming this mode immediately starts a conversion. This start mode is available in all
ADC operating modes.
8.6.3 Edge triggered
An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has
started, additional edge triggers are ignored until the conversion has completed. The edge
triggered start mode is available in all ADC operating modes.
P89LPC92X1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2.1 — 27 August 2012 50 of 75
NXP Semiconductors
P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
8.7 Boundary limits interrupt
Each of the A/D converters has both a high and low boundary limit register. The user may
select whether an interrupt is generated when the conversion result is within (or equal to)
the high and low boundary limits or when the conversion result is outside the boundary
limits. An interrupt will be generated, if enabled, if the result meets the selected interrupt
criteria. The boundary limit may be disabled by clearing the boundary limit interrupt
enable.
An early detection mechanism exists when the interrupt criteria has been selected to be
outside the boundary limits. In this case, after the four MSBs have been converted, these
four bits are compared with the four MSBs of the boundary high and low registers. If the
four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits)
an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt
criteria, the boundary limits will again be compared after all 8 bits have been converted.
The boundary status register (BNDSTA0) flags the channels which caused a boundary
interrupt.
8.8 DAC output to a port pin with high output impedance
The DAC block of ADC1 can be output to a port pin. In this mode, the AD1DAT3 register is
used to hold the value fed to the DAC. After a value has been written to the DAC (written
to AD1DAT3), the DAC output will appear on the channel 3 pin.
8.9 Clock divider
The ADC requires that its internal clock source be in the range of 320 kHz to 8 MHz to
maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is
provided for this purpose.
8.10 Power-down and Idle mode
In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit
Idle mode when the conversion is completed if the A/D interrupt is enabled. In
Power-down mode or Total Power-down mode, the A/D and temperature sensor do not
function. If temperature sensor or the A/D are enabled, they will consume power. Power
can be reduced by disabling temperature sensor and A/D.
P89LPC92X1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2.1 — 27 August 2012 51 of 75
NXP Semiconductors
P89LPC9201/9211/922A1/9241/9251
8-bit microcontroller with 8-bit ADC
9. Limiting values
[1] The following applies to Table 11:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over ambient temperature range unless otherwise specified. All voltages are with respect to V
SS
unless
otherwise noted.
[2] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
Table 11. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
Symbol Parameter Conditions Min Max Unit
T
amb(bias)
bias ambient temperature 55 +125 C
T
stg
storage temperature 65 +150 C
I
OH(I/O)
HIGH-level output current per
input/output pin
-20mA
I
OL(I/O)
LOW-level output current per
input/output pin
-20mA
I
I/Otot(max)
maximum total input/output current - 100 mA
V
xtal
crystal voltage on XTAL1, XTAL2 pin to V
SS
-V
DD
+ 0.5 V
V
n
voltage on any other pin except XTAL1, XTAL2 to V
SS
0.5 +5.5 V
P
tot(pack)
total power dissipation (per package) based on package heat
transfer, not device power
consumption
-1.5W
V
ESD
electrostatic discharge voltage human body model; all pins
[2]
3000 +3000 V
charged device model; all
pins
700 +700 V
Fig 16. Frequency vs. supply voltage
V
DD
(V)
002aae351
system frequency
(MHz)
2.4
18
12
2.7 3.63.33.0
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P89LPC9241FDH,112

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NXP Semiconductors
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Microcontrollers - MCU 8-bit Microcontrollers - MCU MCU 8-Bit CISC 4KB Flash2.5V/3.3V 20Pin
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