FUSB302B
www.onsemi.com
16
Table 11. CURRENT CONSUMPTION
Symbol Parameter V
DD
(V) Conditions
T
A
= −40 to +855C
T
A
= −40 to +1055C (Note 11)
T
J
= −40 to +1255C
Unit
Min Typ Max
Idisable Disabled Current 3.0 to 5.5 Nothing Attached,
No I
2
C Transactions
0.37
5.0 mA
Idisable Disabled Current
(Note 11)
3.0 to 5.5 Nothing Attached,
No I
2
C Transactions
0.37
8.5 mA
Itog Unattached (standby)
Toggle Current
3.0 to 5.5 Nothing attached,
TOGGLE = 1,
PWR[3:0] = 1h,
WAKE_EN = 0,
TOG_SAVE_PWR2:1 = 01
25 40
mA
Ipd_stby_meas BMC PD Standby
Current
3.0 to 5.5 Device Attached, BMC PD
Active But Not Sending or
Receiving Anything,
PWR[3:0] = 7h
40
mA
Table 12. USB PD SPECIFIC PARAMETERS
Symbol Parameter
T
A
= −40 to +855C
T
A
= −40 to +1055C (Note 11)
T
J
= −40 to +1255C
Unit
Min Typ Max
tHardReset If a Soft Reset message fails, a Hard Reset is sent after tHardReset of
CRCReceiveTimer expiring
5 ms
tHardReset
Complete
If the FUSB302B cannot send a Hard Reset within tHardResetComplete
time because of a busy line, then a I_HARDFAIL interrupt is triggered
5 ms
tReceive This is the value for which the CRCReceiveTimer expires.
The CRCReceiveTimer is started upon the last bit of the EOP of the
transmitted packet
0.9 1.1 ms
tRetry Once the CRCReceiveTimer expires, a retry packet has to be sent out
within tRetry time. This time is hard to separate externally from tReceive
since they both happen sequentially with no visible difference in the CC
output
75
ms
tSoftReset If a GoodCRC packet is not received within tReceive for NRETRIES then
a Soft Reset packet is sent within tSoftReset time.
5 ms
tTransmit From receiving a packet, we have to send a GoodCRC in response within
tTransmit time. It is measured from the last bit of the EOP of the received
packet to the first bit sent of the preamble of the GoodCRC packet
195
ms
Table 13. IO SPECIFICATIONS
Symbol Parameter V
DD
(V) Conditions
T
A
= −40 to +855C
T
A
= −40 to +1055C (Note 11)
T
J
= −40 to +1255C
Unit
Min Typ Max
HOST INTERFACE PINS (INT_N)
V
OLINTN
Output Low Voltage 3.0 to 5.5 I
OL
= 4 mA 0.4 V
T
INT_Mask
Time from global interrupt
mask bit cleared to when
INT_N goes LOW
3.0 to 5.5 50
ms
I
2
C INTERFACE PINS – STANDARD, FAST, OR FAST MODE PLUS SPEED MODE (SDA, SCL) (Note 6)
V
ILI2C
Low-Level Input Voltage 3.0 to 5.5 0.51 V
V
IHI2C
High-Level Input Voltage 3.0 to 5.5 1.32 V
FUSB302B
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17
Table 13. IO SPECIFICATIONS
Symbol Unit
T
A
= −40 to +855C
T
A
= −40 to +1055C (Note 11)
T
J
= −40 to +1255C
ConditionsV
DD
(V)Parameter
Symbol Unit
MaxTypMin
ConditionsV
DD
(V)Parameter
I
2
C INTERFACE PINS – STANDARD, FAST, OR FAST MODE PLUS SPEED MODE (SDA, SCL) (Note 6)
V
HYS
Hysteresis of Schmitt
Trigger Inputs
3.0 to 5.5 94 mV
I
I2C
Input Current of SDA and
SCL Pins
3.0 to 5.5
Input Voltage 0.26 V to 2.0 V
−10 10
mA
I
CCTI2C
VDD Current when SDA or
SCL is HIGH
3.0 to 5.5 Input Voltage 1.8 V −10 10
mA
V
OLSDA
Low-Level Output Voltage
(Open-Drain)
3.0 to 5.5 I
OL
= 2 mA 0 0.35 V
I
OLSDA
Low-Level Output Current
(Open-Drain)
3.0 to 5.5 V
OLSDA
= 0.4 V 20 mA
C
I
Capacitance for Each I/O
Pin (Note 7)
3.0 to 5.5 5 pF
6. I
2
C pull up voltage is required to be between 1.71 V and V
DD
.
Table 14. I
2
C SPECIFICATIONS FAST MODE PLUS I
2
C SPECIFICATIONS
Symbol Parameter
Fast Mode Plus
Unit
Min Max
f
SCL
I2C_SCL Clock Frequency 0 1000 kHz
t
HD;STA
Hold Time (Repeated) START Condition
0.26
ms
t
LOW
Low Period of I2C_SCL Clock 0.5
ms
t
HIGH
High Period of I2C_SCL Clock 0.26
ms
t
SU;STA
Set-up Time for Repeated START Condition 0.26
ms
t
HD;DAT
Data Hold Time 0
ms
t
SU;DAT
Data Set-up Time 50 ns
t
r
Rise Time of I2C_SDA and I2C_SCL Signals (Note 7) 120 ns
t
f
Fall Time of I2C_SDA and I2C_SCL Signals (Note 7) 6 120 ns
t
SU;STO
Set−up Time for STOP Condition 0.26
ms
t
BUF
Bus-Free Time between STOP and START Conditions (Note 7) 0.5
ms
t
SP
Pulse Width of Spikes that Must Be Suppressed by the Input Filter 0 50 ns
C
b
Capacitive Load for each Bus Line (Note 7) 550 pF
t
VD−DAT
Data Valid Time for Data from SCL LOW to SDA HIGH or LOW Output (Note 7) 0 0.45
ms
t
VD−ACK
Data Valid Time for acknowledge from SCL LOW to SDA HIGH or LOW Output
(Note 7)
0 0.45
ms
V
nL
Noise Margin at the LOW Level (Note 7) 0.2 V
V
nH
Noise Margin at the HIGH Level (Note 7) 0.4 V
7. Guaranteed by Characterization and/or Design. Not production tested.
FUSB302B
www.onsemi.com
18
Figure 17. Definition of Timing for Full-Speed Mode Devices on the I
2
C Bus
Table 15. I
2
C SLAVE ADDRESS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FUSB302BUCX,
FUSB302BMPX,
FUSB302BVMPX
0 1 0 0 0 1 0 R/W
FUSB302B01MPX 0 1 0 0 0 1 1 R/W
FUSB302B10MPX 0 1 0 0 1 0 0 R/W
FUSB302B11MPX 0 1 0 0 1 0 1 R/W
Table 16. REGISTER DEFINITIONS (Notes 8 and 9)
Address
Register
Name
Type
Reg
Value
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x01 Device ID R 9X Version ID[3:0] Product ID[1:0] Revision ID[1:0]
0x02 Switches0 R/W 3 PU_EN2 PU_EN1 VCONN_
CC2
VCONN_
CC1
MEAS_
CC2
MEAS_
CC1
PDWN2 PDWN1
0x03 Switches1 R/W 20 POWER
ROLE
SPEC
REV1
SPEC
REV0
DATA
ROLE
AUTO_
CRC
TXCC2 TXCC1
0x04 Measure R/W 31 MEAS_
VBUS
MDAC5 MDAC4 MDAC3 MDAC2 MDAC1 MDAC0
0x05 Slice R/W 60 SDAC_
HYS1
SDAC_
HYS2
SDAC5 SDAC4 SDAC3 SDAC2 SDAC1 SDAC0
0x06 Control0 R/W/C 24 TX_
FLUSH
INT_MASK HOST_
CUR1
HOST_
CUR0
AUTO_
PRE
TX_START
0x07 Control1 R/W/C 0 ENSOP
2DB
ENSOP
1DB
BIST_
MODE2
RX_
FLUSH
ENSOP2 ENSOP1
0x08 Control2 R/W 2 TOG_
SAVE_
PWR2
TOG_
SAVE_
PWR1
TOG_RD_
ONLY
WAKE_EN MODE[1:0] TOGGLE
0x09 Control3 R/W 6
SEND_
HARD_
BIST_
TMODE
AUTO_
HARD
RESET
AUTO_
N_RETRIES[1:0] AUTO_
RETRY
RESET SOFTRES
ET

FUSB302BUCX

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC USB TYPE C CTLR PROGR 9WLCSP
Lifecycle:
New from this manufacturer.
Delivery:
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