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FUSB302BUCX

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
FUSB302B
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22
Table 23. CONTROL1
(Address: 07h; Reset Value: 0x0000_0000; Type: (see column below))
Bit #
Name R/W/C Size (Bits) Description
7 Reserved N/A 1 Do Not Use
6 ENSOP2DB R/W 1 1: Enable SOP”_DEBUG (SOP double prime debug) packets
0: Ignore SOP”_DEBUG (SOP double prime debug) packets
5 ENSOP1DB R/W 1 1: Enable SOP _DEBUG (SOP prime debug) packets
0: Ignore SOP
_DEBUG (SOP prime debug) packets
4 BIST_MODE2 R/W 1 1: Sent BIST Mode 01s pattern for testing
3 Reserved N/A 1 Do Not Use
2 RX_FLUSH W/C 1 1: Self clearing bit to flush the content of the receive FIFO
1 ENSOP2 R/W 1 1: Enable SOP”(SOP double prime) packets
0: Ignore SOP”(SOP double prime) packets
0 ENSOP1 R/W 1 1: Enable SOP (SOP prime) packets
0: Ignore SOP
(SOP prime) packets
Table 24. CONTROL2
(Address: 08h; Reset Value: 0x0000_0010; Type: (see column below))
Bit #
Name R/W/C Size (Bits) Description
7:6 TOG_SAVE_PWR2:
TOG_SAVE_PWR1
N/A 2 00: Don’t go into the DISABLE state after one cycle of toggle
01: Wait between toggle cycles for t
DIS
time of 40 ms
10: Wait between toggle cycles for t
DIS
time of 80 ms
11: Wait between toggle cycles for t
DIS
time of 160 ms
5 TOG_RD_ONLY R/W 1 1: When TOGGLE=1 only Rd values will cause the TOGGLE
state machine to stop toggling and trigger the I_TOGGLE
interrupt
0: When TOGGLE=1, Rd and Ra values will cause the TOGGLE
state machine to stop toggling
4 Reserved N/A 1 Do Not Use
3 WAKE_EN R/W 1 1: Enable Wake Detection functionality if the power state is
correct
0: Disable Wake Detection functionality
2:1 MODE R/W 2 11: Enable SRC polling functionality if TOGGLE=1
10: Enable SNK polling functionality if TOGGLE=1
01: Enable DRP polling functionality if TOGGLE=1
00: Do Not Use
0 TOGGLE R/W 1 1: Enable DRP, SNK or SRC Toggle autonomous functionality
0: Disable DRP, SNK and SRC Toggle functionality
FUSB302B
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23
Table 25. CONTORL3
(Address: 09h; Reset Value: 0x0000_0110; Type: (see column below))
Bit #
Name R/W/C Size (Bits) Description
7 Reserved N/A 1 Do Not Use
6 SEND_HARD_RESET W/C 1 1: Send a hard reset packet (highest priority)
0: Don’t send a soft reset packet
5 BIST_TMODE R/W 1 1: BIST mode. Receive FIFO is cleared immediately after
sending GoodCRC response
0: Normal operation, All packets are treated as usual
4 AUTO_HARDRESET R/W 1 1: Enable automatic hard reset packet if soft reset fail
0: Disable automatic hard reset packet if soft reset fail
3 AUTO_SOFTRESET R/W 1 1: Enable automatic soft reset packet if retries fail
0: Disable automatic soft reset packet if retries fail
2:1 N_RETRIES[1:0] R/W 2 11: Three retries of packet (four total packets sent)
10: Two retries of packet (three total packets sent)
01: One retry of packet (two total packets sent)
00: No retries (similar to disabling auto retry)
0 AUTO_RETRY R/W 1 1: Enable automatic packet retries if GoodCRC is not received
0: Disable automatic packet retries if GoodCRC not received
Table 26. MASK
(Address: 0Ah; Reset Value: 0x0000_0000; Type: Read/Write)
Bit #
Name R/W/C Size (Bits) Description
7 M_VBUSOK R/W 1 1: Mask I_VBUSOK interrupt bit
0: Do not mask
6 M_ACTIVITY R/W 1 1: Mask interrupt for a transition in CC bus activity
0: Do not mask
5 M_COMP_CHNG R/W 1 1: Mask I_COMP_CHNG interrupt for change is the value of
COMP, the measure comparator
0: Do not mask
4 M_CRC_CHK R/W 1 1: Mask interrupt from CRC_CHK bit
0: Do not mask
3 M_ALERT R/W 1 1: Mask the I_ALERT interrupt bit
0: Do not mask
2 M_WAKE R/W 1 1: Mask the I_WAKE interrupt bit
0: Do not mask
1 M_COLLISION R/W 1 1: Mask the I_COLLISION interrupt bit
0: Do not mask
0 M_BC_LVL R/W 1 1: Mask a change in host requested current level
0: Do not mask
Table 27. POWER
(Address: 0Bh; Reset Value: 0x0000_0001; Type: Read/Write)
Bit #
Name R/W/C Size (Bits) Description
7:4 Reserved N/A 4 Do Not Use
3:0 PWR[3:0] R/W 4 Power enables:
PWR[0]: Bandgap and wake circuit
PWR[1]: Receiver powered and current references for Measure
block
PWR[2]: Measure block powered
PWR[3]: Enable internal oscillator
FUSB302B
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24
Table 28. RESET
(Address: 0Ch; Reset Value: 0x0000_0000; Type: Write/Clear)
Bit #
Name R/W/C Size (Bits) Description
7:2 Reserved N/A 6 Do Not Use
1 PD_RESET W/C 1 1: Reset just the PD logic for both the PD transmitter and
receiver
0 SW_RES W/C 1 1: Reset the FUSB302B including the I
2
C registers to their
default values
Table 29. OCPREG
(Address: 0Dh; Reset Value: 0x0000_1111; Type: Read/Write)
Bit # Name R/W/C Size (Bits) Description
7:4 Reserved N/A 4 Do Not Use
3 OCP_RANGE R/W 1 1: OCP range between 100−800 mA (max_range = 800 mA)
0: OCP range between 10−80 mA (max_range = 80 mA)
2:0 OCP_CUR2,
OCP_CUR1,
OCP_CUR0
R/W 3 111: max_range (see bit definition above for OCP_RANGE)
110: 7 × max_range / 8
101: 6 × max_range / 8
100: 5 × max_range / 8
011: 4 × max_range / 8
010: 3 × max_range / 8
001: 2 × max_range / 8
000: max_range / 8
Table 30. MASKA
(Address: 0Eh; Reset Value: 0x0000_0000; Type: Read/Write)
Bit # Name R/W/C Size (Bits) Description
7 M_OCP_TEMP R/W 1 1: Mask the I_OCP_TEMP interrupt
6 M_TOGDONE R/W 1 1: Mask the I_TOGDONE interrupt
5 M_SOFTFAIL R/W 1 1: Mask the I_SOFTFAIL interrupt
4 M_RETRYFAIL R/W 1 1: Mask the I_RETRYFAIL interrupt
3 M_HARDSENT R/W 1 1: Mask the I_HARDSENT interrupt
2 M_TXSENT R/W 1 1: Mask the I_TXSENT interrupt
1 M_SOFTRST R/W 1 1: Mask the I_SOFTRST interrupt
0 M_HARDRST R/W 1 1: Mask the I_HARDRST interrupt
Table 31. MASKB
(Address: 0Fh; Reset Value: 0x0000_0000; Type: Read/Write)
Bit #
Name R/W/C Size (Bits) Description
7:1 Reserved N/A 6 Do Not Use
0 M_GCRCSENT R/W 1 1: Mask the I_GCRCSENT interrupt
Table 32. CONTROL4
(Address: 00h; Reset Value: 0x0000_0000; Type: Read/Write)
Bit # Name R/W/C Size (Bits) Description
7:1 Reserved N/A 6 Do Not Use
0 TOG_EXIT_AUD R/W 1 1: In auto Rd only Toggle mode, stop Toggle at Audio accessory
(Ra on both CC)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

FUSB302BUCX

Mfr. #:
Buy FUSB302BUCX
Manufacturer:
ON Semiconductor
Description:
IC USB TYPE C CTLR PROGR 9WLCSP
Lifecycle:
New from this manufacturer.
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